Description

Abstract

Two general methods exist for computation of the algorithms. The first method is ASIC which can implement the desired algorithms to hardware. These types of equipment are made for each specific algorithm, so they are fast and efficient. But after building the circuit, they do not change. The second way is using microprocessors that are much more flexible. They run a series of commands and system software can be changed without changing the hardware. But, as an ASIC they are not designed for a particular application, so they are not flexible. Reconfigurable systems have been developed in such a way to help reduce the gap between hardware and software and also, achieve a much higher performance and flexibility for software and hardware. Therefore, in this project, first, a brief history of the development of the reconfigurable system is presented. After that, the concept of reconfigurable and all related designs are presented. The design of on-chip reconfigurable FPGA is presented. Design features of a programming language based on VHDL are presented. Finally, we present the hardware and software system that has the capability of the reconfigurable method, and the system uses reconfigurable parallel processing which increases performance.

Reference:

  1. A.Wang Lie, Wu Feng-yan “Dynamic partial reconfiguration in FPGAs,” 2009 Third International Symposium on Intelligent Information Technology Application.
  2. A.Trailokya Nath Sasamal, Anand Mohan, 2011 . “a specially designed transient faults injection technique at the vhdl level and modeling,” ijrras 9 (2) ● November.
  3. B. Maamar Touiza , Gilberto Ochoa-Ruiz, 2012. “A novel methodology for accelerating bitstream relocation in partially reconfigurable systems,” Microprocessors and Microsystems journal .
  4. B. Krill, A.Ahmad, 2010. “An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores,” Signal Processing: Image Communication 25.
  5. C.Abhishek Tiwari, 2012. “A Partial Reconfiguration based Approach for Frequency Synthesis using FPGA,” International Conference on Communication Technology and System Design 2011, Procedia Engineering 30 .
  6. D. Christopher T. Rathgeb, 2009. “Secure processing using dynamic partial reconfiguration,” CSIIRW ’09, April 13-15, Oak Ridge, Tennessee, USA Copyright ACM.
  7. K. KE˛PA, F. MORGAN, and K. Ko´Sciuszkiewicz. “Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems,” National University of Ireland, Universit’ at Karlsruhe Institute of Technology (KIT).
  8. L.Dirk Koch, Christian Beckhoff, and Jim Torresen, 2010. “Zero logic overhead integration of partially reconfigurable modules,” SBCCI’10, São Paulo, Brazil. Copyright 2010 ACM.
  9. L.Seema Verma. 2011. “Improvement in RSA Cryptosystem, journal of advances in information technology, VOL. 2, NO. 3.
  10. M.Kyprianos Papadimitriou And Apostolos Dollas, 2011. “Performance of partial reconfiguration in FPGA systems A survey and a cost model,” ACM Transactions on Reconfigurable Technology and Systems, Vol. 4, No. 4, Article 36, Publication date: December.
  11. .José Rodrigo Azambuja August, 30–September 2, 2011. “Using Dynamic Partial Reconfiguration to Detect SEEs in SBCCI’11, João Pessoa, Brazil. Copyright 2011 ACM.
  12. O.Robert S. Boyer And J Strother Moore, 2012. “Proof Checking The Rsa Public Key Encryption Algorithm1,”  Mathematical Association of America is collaborating with JSTOR to digitize.
  1. P.Lubos Gaspar, October 2012. “Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities,” ACM Transactions on Reconfigurable Technology and Systems, Vol. 5, No. 3, Article 16, Publication date.
  2. P.Ivan Gonzalez, 2012. “Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture,” Journal of Systems Architecture 58.
  3. R.Daniel Llamocca, Member, IEEE, and Marios Pattichis, Senior Member, IEEE, MARCH 2013. “A Dynamically Reconfigurable Pixel Processor System Based on PowerEnergy-Performance-Accuracy Optimization,” Ieee Transactions On Circuits And Systems For Video Technology, Vol. 23, No. 3.
  4. Z.Qianming Yang, 2013. “Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration,” J Supercomput.

 

Output of Modelsim software:

adder :

out_addder_modelsim

multiplier :

out_multiplier_modelsim

divider :

out_divider_modelsim

ALU :

out_ALU_modelsim

 

 

 

Synthesis Result of ISE software :

adder carry look :

=========================================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : adder_Carry_Look_ahead.ngr

Top Level Output File Name         : adder_Carry_Look_ahead

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : No

Design Statistics

# IOs                              : 98

Cell Usage :

# BELS                             : 64

#      LUT3                        : 64

# IO Buffers                       : 98

#      IBUF                        : 65

#      OBUF                        : 33

=========================================================================

Device utilization summary:

—————————

Selected Device : 3s50pq208-5

Number of Slices:                       37  out of    768     4%

Number of 4 input LUTs:                 64  out of   1536     4%

Number of IOs:                          98

Number of bonded IOBs:                  98  out of    124    79%

—————————

Partition Resource Summary:

—————————

No Partitions were found in this design.

—————————

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

——————

No clock signals found in this design

Asynchronous Control Signals Information:

—————————————-

No asynchronous control signals found in this design

Timing Summary:

—————

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 47.847ns

Timing Detail:

————–

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 1153 / 33

————————————————————————-

Delay:               47.847ns (Levels of Logic = 34)

Source:            x_in<0> (PAD)

Destination:       sum<31> (PAD)

Data Path: x_in<0> to sum<31>

Gate     Net

) Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

 

 

 

 

 

 

 

 

 

 

 

 

multiplier :

===============================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : multiplier_unsigned.ngr

Top Level Output File Name         : multiplier_unsigned

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : No

Design Statistics

# IOs                              : 64

Cell Usage :

# BELS                             : 1016

#      GND                         : 1

#      LUT1                        : 1

#      LUT2                        : 30

#      LUT3                        : 185

#      LUT4                        : 291

#      MUXCY                       : 240

#      MUXF5                       : 28

#      XORCY                       : 240

# IO Buffers                       : 64

#      IBUF                        : 32

#      OBUF                        : 32

===============================================================

Device utilization summary:

—————————

Selected Device : 3s50pq208-5

Number of Slices:                      270  out of    768    35%

Number of 4 input LUTs:                507  out of   1536    33%

Number of IOs:                          64

Number of bonded IOBs:                  64  out of    124    51%

—————————

Partition Resource Summary:

—————————

No Partitions were found in this design.

—————————

===============================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

——————

No clock signals found in this design

Asynchronous Control Signals Information:

—————————————-

No asynchronous control signals found in this design

Timing Summary:

—————

Speed Grade: -5

 

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 48.993ns

 

Timing Detail:

————–

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 134597834529761 / 32

————————————————————————-

Delay:               48.993ns (Levels of Logic = 62)

Source:            b_unsigned<0> (PAD)

Destination:       mult_unsigned<30> (PAD)

Data Path: b_unsigned<0> to mult_unsigned<30>

Gate     Net

Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

 

 

 

 

 

 

 

 

 

 

 

 

 

divider :

===============================================================

*                            Final Report                               *

===============================================================

Final Results

RTL Top Level Output File Name     : n_Bit_Divider.ngr

Top Level Output File Name         : n_Bit_Divider

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : No

Design Statistics

# IOs                              : 64

Cell Usage :

# BELS                             : 3044

#      GND                         : 1

#      INV                         : 46

#      LUT2                        : 88

#      LUT3                        : 496

#      LUT4                        : 864

#      MULT_AND                    : 57

#      MUXCY                       : 995

#      VCC                         : 1

#      XORCY                       : 496

# IO Buffers                       : 64

#      IBUF                        : 32

#      OBUF                        : 32

===============================================================

Device utilization summary:

————————–

Selected Device : 3s50pq208-5

Number of Slices:                      798  out of    768   103% (*)

Number of 4 input LUTs:               1494  out of   1536    97%

Number of IOs:                          64

Number of bonded IOBs:                  64  out of    124    51%

WARNING:Xst:1336 –  (*) More than 100% of Device resources are used

—————————

Partition Resource Summary:

—————————

No Partitions were found in this design.

—————————

=========================================================================

TIMING REPORT

 

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

——————

No clock signals found in this design

Asynchronous Control Signals Information:

—————————————-

No asynchronous control signals found in this design

Timing Summary:

—————

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 177.225ns

Timing Detail:

————–

All values displayed in nanoseconds (ns)

===============================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 9302334276068681700000000000000000000000000000000000000 / 32

————————————————————————-

Delay:               177.225ns (Levels of Logic = 536)

Source:            y_in<0> (PAD)

Destination:       frac<0> (PAD)

Data Path: y_in<0> to frac<0>

Gate     Net

Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALU :

===============================================================

*                            Final Report                               *

===============================================================

Final Results

RTL Top Level Output File Name     : ALU.ngr

Top Level Output File Name         : ALU

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : No

Design Statistics

# IOs                              : 60

Cell Usage :

# BELS                             : 1040

#      GND                         : 1

#      INV                         : 15

#      LUT1                        : 1

#      LUT2                        : 82

#      LUT3                        : 164

#      LUT4                        : 272

#      MULT_AND                    : 25

#      MUXCY                       : 289

#      MUXF5                       : 21

#      VCC                         : 1

#      XORCY                       : 169

# IO Buffers                       : 60

#      IBUF                        : 19

#      OBUF                        : 41

===============================================================

Device utilization summary:

—————————

Selected Device : 3s50pq208-5

Number of Slices:                      289  out of    768    37%

Number of 4 input LUTs:                534  out of   1536    34%

Number of IOs:                          60

Number of bonded IOBs:                  60  out of    124    48%

—————————

Partition Resource Summary:

—————————

No Partitions were found in this design.

—————————

===============================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

——————

No clock signals found in this design

Asynchronous Control Signals Information:

—————————————-

No asynchronous control signals found in this design

Timing Summary:

—————

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 83.108ns

Timing Detail:

————–

All values displayed in nanoseconds (ns)

===============================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 83353851265305404000000 / 41

————————————————————————-

Delay:               83.108ns (Levels of Logic = 142)

Source:            datain2<5> (PAD)

Destination:       frac<0> (PAD)

Data Path: datain2<5> to frac<0>

 

 

 

 

 

 

 

Internal Circuit of multiplier :

multiplier

2 reviews for VHDL Code for Design and implementation of a reconfiguration microprocessor

  1. Nicholas

    I’m very grateful for this project, and I really enjoyed it.

  2. ELLIOTT

    A fantastic project!

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