In the last four decades, the incorporation of analog, digital and mixed-signal integrated circuits (IC) using Complementary Metal Oxide Semiconductor (CMOS) technology has been dramatically increasing and is improving almost every aspect of modern life. Furthermore, the continuous advances in CMOS Very Large System Integration (VLSI) technology allow higher integration densities and the increasing number of subsystems in a single chip results in higher speed execution and lower power consumption. Therefore, the increasing digitalization in electronic circuits across a wide range of battery-operated applications where reliability and power dissipation are critical requires Digital to Analog Converters (DACs) with higher resolution and lower power consumption.
The present work analyzes the operation and response of ΔΣ DAC at subthreshold voltage levels. At subthreshold regime, the voltage supply is far below traditional voltage levels. Additionally, subthreshold operations have the advantage over other techniques to achieve the optimum operating point per operation and thereby reduce the overall power dissipation. The ΔΣ DAC was designed in TSMC 0.25 μm CMOS technology.
The main block diagram is shown in the following figure :