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	<title>Speech Recognition Archives &#8212; MATLAB Number ONE</title>
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	<title>Speech Recognition Archives &#8212; MATLAB Number ONE</title>
	<link>https://matlab1.com/category/speech-recognition/</link>
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	<item>
		<title>Hidroaysen And Patagonia</title>
		<link>https://matlab1.com/hidroaysen-and-patagonia/</link>
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		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Tue, 14 Nov 2017 13:15:19 +0000</pubDate>
				<category><![CDATA[Communication]]></category>
		<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[gross domestic product (GDP)]]></category>
		<category><![CDATA[HidroAysén]]></category>
		<category><![CDATA[neoliberalism]]></category>
		<category><![CDATA[nternational Monetary Fund (IMF)]]></category>
		<category><![CDATA[Patagonia without Dams]]></category>
		<category><![CDATA[United Nations (UN)]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2981</guid>

					<description><![CDATA[<p>introfuction  In 2006, amid a national energy crisis, Chilean utility companies Colbún and Endesa S.A. announced a joint venture called HidroAysén, a hydroelectric project proposing to construct five megadams on the Baker and Pascua rivers in Chile’s southernmost region of Patagonia. The majority of the Chilean public opposed the project on environmental and social grounds, [&#8230;]</p>
<p>The post <a href="https://matlab1.com/hidroaysen-and-patagonia/">Hidroaysen And Patagonia</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>PCI Express Transmission Discussion About Architecture Design For A Neural Spike-Based Data Reduction Platform</title>
		<link>https://matlab1.com/pci-express-transmission-discussion-architecture-design-neural-spike-based-data-reduction-platform/</link>
					<comments>https://matlab1.com/pci-express-transmission-discussion-architecture-design-neural-spike-based-data-reduction-platform/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Sun, 12 Nov 2017 11:05:47 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[BFR]]></category>
		<category><![CDATA[DMA-based design]]></category>
		<category><![CDATA[FIFO]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[maximum bursting rate]]></category>
		<category><![CDATA[SpkAcc]]></category>
		<category><![CDATA[transmission rate]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2809</guid>

					<description><![CDATA[<p>The PCIe transmission using Xillybus IPcore was relatively a straightforward solution for the transmission from the FPGA to the host PC. The Xillybus IPcore provides the necessary DMA-based design and the software driver to handle the data reception at the host. It was convenient for observing the data processed by the hardware design and evaluating [&#8230;]</p>
<p>The post <a href="https://matlab1.com/pci-express-transmission-discussion-architecture-design-neural-spike-based-data-reduction-platform/">PCI Express Transmission Discussion About Architecture Design For A Neural Spike-Based Data Reduction Platform</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>Discussion About Architecture Design For A Neural Spike-Based Data Reduction Platform</title>
		<link>https://matlab1.com/discussion-architecture-design-neural-spike-based-data-reduction-platform/</link>
					<comments>https://matlab1.com/discussion-architecture-design-neural-spike-based-data-reduction-platform/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Sun, 12 Nov 2017 10:52:12 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[JEDEC]]></category>
		<category><![CDATA[MGTs]]></category>
		<category><![CDATA[Multi-Gigabit transceivers]]></category>
		<category><![CDATA[Neural Spike-Based Data]]></category>
		<category><![CDATA[Xilinx]]></category>
		<category><![CDATA[Zync]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2806</guid>

					<description><![CDATA[<p>The research presented in this dissertation was motivated by a long term goal of monitoring the electrical activity of thousands of neurons, in an effort to decipher the brain activity. Recording thousands of neural signals may provide some insight in what Santiago Ramón y Cajal, the father of modern neuroscience, called &#8220;the impenetrable jungle where [&#8230;]</p>
<p>The post <a href="https://matlab1.com/discussion-architecture-design-neural-spike-based-data-reduction-platform/">Discussion About Architecture Design For A Neural Spike-Based Data Reduction Platform</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>Testing The Integration of Twenty Spike-Detection Units with PCIe Transmission</title>
		<link>https://matlab1.com/testing-integration-twenty-spike-detection-units-pcie-transmission/</link>
					<comments>https://matlab1.com/testing-integration-twenty-spike-detection-units-pcie-transmission/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Sun, 12 Nov 2017 10:40:54 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[BRAMs]]></category>
		<category><![CDATA[FSM]]></category>
		<category><![CDATA[NEO]]></category>
		<category><![CDATA[PCIe]]></category>
		<category><![CDATA[Queue Write Control]]></category>
		<category><![CDATA[SDU]]></category>
		<category><![CDATA[Select Detector Unit]]></category>
		<category><![CDATA[WR]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2794</guid>

					<description><![CDATA[<p>In Testing Data Transmission using Real Data Recordings the PCIe data transmission was tested using real neuronal recordings from 2550 channels. The spike times were stored on BRAMs and a model was designed to mimic the Spike Detection Unit function. The design affiliated 48 words to every spike detected, and sent it via PCIe to [&#8230;]</p>
<p>The post <a href="https://matlab1.com/testing-integration-twenty-spike-detection-units-pcie-transmission/">Testing The Integration of Twenty Spike-Detection Units with PCIe Transmission</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>Testing Data Transmission using Real Data Recordings</title>
		<link>https://matlab1.com/testing-data-transmission-using-real-data-recordings/</link>
					<comments>https://matlab1.com/testing-data-transmission-using-real-data-recordings/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Sat, 11 Nov 2017 17:43:51 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[ChipScope]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[FSM]]></category>
		<category><![CDATA[MEA]]></category>
		<category><![CDATA[Mean Firing Rate]]></category>
		<category><![CDATA[MFR]]></category>
		<category><![CDATA[spike wave shape]]></category>
		<category><![CDATA[TDM]]></category>
		<category><![CDATA[Xillybus IPcore]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2698</guid>

					<description><![CDATA[<p>After testing the data transmission from FPGA to the host, using continuous incrementing counter data, it was desirable to evaluate the data transmission and queue depths needed when the system is handling real neuronal firing rates on hardware. As the spike detection platform is not connected to real data acquisition system, the data was saved [&#8230;]</p>
<p>The post <a href="https://matlab1.com/testing-data-transmission-using-real-data-recordings/">Testing Data Transmission using Real Data Recordings</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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			</item>
		<item>
		<title>Xillybus IP core Implementation</title>
		<link>https://matlab1.com/xillybus-ip-core-implementation/</link>
					<comments>https://matlab1.com/xillybus-ip-core-implementation/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Sat, 11 Nov 2017 16:58:30 +0000</pubDate>
				<category><![CDATA[MATLAB]]></category>
		<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[ChipScope]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[TLP]]></category>
		<category><![CDATA[Transaction Layer packet]]></category>
		<category><![CDATA[Virtex]]></category>
		<category><![CDATA[Xilinx]]></category>
		<category><![CDATA[Xillybus]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2673</guid>

					<description><![CDATA[<p>The Xillybus IP core was implemented on a Virtex-5 FPGA on a Xilinx xupv5lx110t board. The core ports were connected to ChipScope integrated logic analyzer for on-chip testing. Before integrating the Xillybus IP core into the spike-based data reduction platform, its performance was first tested by transmitting predefined data read from a ROM on the [&#8230;]</p>
<p>The post <a href="https://matlab1.com/xillybus-ip-core-implementation/">Xillybus IP core Implementation</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<title>Hardware Implementation And System Evaluation of Spike-Based Data Reduction Platform</title>
		<link>https://matlab1.com/hardware-implementation-system-evaluation-spike-based-data-reduction-platform/</link>
					<comments>https://matlab1.com/hardware-implementation-system-evaluation-spike-based-data-reduction-platform/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Fri, 10 Nov 2017 20:19:24 +0000</pubDate>
				<category><![CDATA[MATLAB]]></category>
		<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[BRAM]]></category>
		<category><![CDATA[GTP]]></category>
		<category><![CDATA[MGT Transceivers]]></category>
		<category><![CDATA[SMA]]></category>
		<category><![CDATA[TXDATA]]></category>
		<category><![CDATA[Xilinx ChipScope]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2619</guid>

					<description><![CDATA[<p>This chapter details the hardware implementation of the platform design, and how the testing of each building block was performed. The spike detection processing modules were designed using Verilog HDL code. They were simulated using Xilinx® ISim for functional verification. The Xilinx® Core generator was used to configure the integrated blocks on the FPGA such [&#8230;]</p>
<p>The post <a href="https://matlab1.com/hardware-implementation-system-evaluation-spike-based-data-reduction-platform/">Hardware Implementation And System Evaluation of Spike-Based Data Reduction Platform</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>Simulation Results of Transmitting the APs from the Output Buffers to a Host PC</title>
		<link>https://matlab1.com/simulation-results-transmitting-aps-output-buffers-host-pc/</link>
					<comments>https://matlab1.com/simulation-results-transmitting-aps-output-buffers-host-pc/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Fri, 10 Nov 2017 19:26:05 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[FIFO]]></category>
		<category><![CDATA[hippocampus]]></category>
		<category><![CDATA[multichannel bursting]]></category>
		<category><![CDATA[PCIe]]></category>
		<category><![CDATA[TDM]]></category>
		<category><![CDATA[TR]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2617</guid>

					<description><![CDATA[<p>The simulation results of the neuronal firing data transmission model show that the bursting and super-bursting times present the most critical intervals for the system. In BMI applications, for example the queuing-based transmission delay must fall below 10 milliseconds. Setting a value for the transmission rate will not only depend on the limits for queuing-based [&#8230;]</p>
<p>The post <a href="https://matlab1.com/simulation-results-transmitting-aps-output-buffers-host-pc/">Simulation Results of Transmitting the APs from the Output Buffers to a Host PC</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>Spike Detection Units and Setup</title>
		<link>https://matlab1.com/spike-detection-units-se/</link>
					<comments>https://matlab1.com/spike-detection-units-se/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Fri, 10 Nov 2017 19:18:37 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[CH]]></category>
		<category><![CDATA[FIFO]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[IB]]></category>
		<category><![CDATA[intrinsically bursting]]></category>
		<category><![CDATA[MEA]]></category>
		<category><![CDATA[neurons and chattering]]></category>
		<category><![CDATA[PCI]]></category>
		<category><![CDATA[Regular Spiking]]></category>
		<category><![CDATA[RS]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2585</guid>

					<description><![CDATA[<p>Integration of Several Spike Detection Units: The total number of channels to be processed is reconfigurable. According to the neural signal processing algorithm used, the longest process applied after sample reading was to copy the first 16 samples of an AP. This procedure required nineteen clock cycles. To have an optimum hardware usage, twenty spike-based [&#8230;]</p>
<p>The post <a href="https://matlab1.com/spike-detection-units-se/">Spike Detection Units and Setup</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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		<item>
		<title>Platform Designing of Spike-Based Data</title>
		<link>https://matlab1.com/platform-designing-spike-based-data/</link>
					<comments>https://matlab1.com/platform-designing-spike-based-data/#respond</comments>
		
		<dc:creator><![CDATA[global MATLAB]]></dc:creator>
		<pubDate>Fri, 10 Nov 2017 17:33:11 +0000</pubDate>
				<category><![CDATA[Speech Recognition]]></category>
		<category><![CDATA[Autonomous Threshold selection]]></category>
		<category><![CDATA[BRAM]]></category>
		<category><![CDATA[MEA]]></category>
		<category><![CDATA[NEO]]></category>
		<category><![CDATA[Neural Spike Detection]]></category>
		<category><![CDATA[Spike-based Data Reduction Unit]]></category>
		<guid isPermaLink="false">https://matlab1.com/?p=2548</guid>

					<description><![CDATA[<p>System Overview: The Neural Spike Detection platform receives time division multiplexed serial samples from a high number of neural recording channels at the multi gigabit receiver port of the FPGA. The receiver performs deserialization of the data and ensures correct sample-word alignment. The system affiliates each sample to its source channel and performs spike detection. [&#8230;]</p>
<p>The post <a href="https://matlab1.com/platform-designing-spike-based-data/">Platform Designing of Spike-Based Data</a> appeared first on <a href="https://matlab1.com">MATLAB Number ONE</a>.</p>
]]></description>
		
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