Signal Processing

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Size of OutputSigned is ,number,integer} and size of OutputSignals is number,integer}. OutputSigned must have one elem

Last post by mamorani « Sat Mar 13, 2021 11:28 pm

by mamorani » Sat Mar 13, 2021 11:28 pm

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195 Views

Last post by mamorani
Sat Mar 13, 2021 11:28 pm
Connection property has too many argument for a socket connection

Last post by mamorani « Sat Mar 13, 2021 11:28 pm

by mamorani » Sat Mar 13, 2021 11:28 pm

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223 Views

Last post by mamorani
Sat Mar 13, 2021 11:28 pm
Inputs are not frames. When FrameBasedProcessing is on, the inputs must be frames (column vectors).

Last post by mamorani « Sat Mar 13, 2021 11:27 pm

by mamorani » Sat Mar 13, 2021 11:27 pm

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214 Views

Last post by mamorani
Sat Mar 13, 2021 11:27 pm
A mismatch in sample time between the original and generated model was detected on port " This may cause some mismatche

Last post by mamorani « Sat Mar 13, 2021 11:26 pm

by mamorani » Sat Mar 13, 2021 11:26 pm

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213 Views

Last post by mamorani
Sat Mar 13, 2021 11:26 pm
Variable step size is not supported by SystemVerilog DPI testbench generation

Last post by mamorani « Sat Mar 13, 2021 11:25 pm

by mamorani » Sat Mar 13, 2021 11:25 pm

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196 Views

Last post by mamorani
Sat Mar 13, 2021 11:25 pm
Customization of "VHDL library name" option is not supported,please set it to the default "work

Last post by mamorani « Sat Mar 13, 2021 11:24 pm

by mamorani » Sat Mar 13, 2021 11:24 pm

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200 Views

Last post by mamorani
Sat Mar 13, 2021 11:24 pm
HDL code generation option "Use trigger signal as clock" is not supported. Turn it off in configuration parameters.

Last post by mamorani « Sat Mar 13, 2021 11:24 pm

by mamorani » Sat Mar 13, 2021 11:24 pm

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229 Views

Last post by mamorani
Sat Mar 13, 2021 11:24 pm
Found Inport at the root-level of the generated model. Input port is not supported by SystemVerilog DPI testbench

Last post by mamorani « Sat Mar 13, 2021 11:24 pm

by mamorani » Sat Mar 13, 2021 11:24 pm

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198 Views

Last post by mamorani
Sat Mar 13, 2021 11:24 pm
Start checking model compatibility with SystemVerilog DPI testbench

Last post by mamorani « Sat Mar 13, 2021 11:23 pm

by mamorani » Sat Mar 13, 2021 11:23 pm

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204 Views

Last post by mamorani
Sat Mar 13, 2021 11:23 pm
SystemVerilog DPI test bench only supports native floating point.In order to generate the test bench with single data ty

Last post by mamorani « Sat Mar 13, 2021 11:23 pm

by mamorani » Sat Mar 13, 2021 11:23 pm

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208 Views

Last post by mamorani
Sat Mar 13, 2021 11:23 pm
There are some known issues with mixed language simulation in Vivado Simulator, it is recommended to set 'TargetLanguage

Last post by mamorani « Sat Mar 13, 2021 11:22 pm

by mamorani » Sat Mar 13, 2021 11:22 pm

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215 Views

Last post by mamorani
Sat Mar 13, 2021 11:22 pm
Simulator is not supported by SystemVerilog DPI testbench generation.

Last post by mamorani « Sat Mar 13, 2021 11:22 pm

by mamorani » Sat Mar 13, 2021 11:22 pm

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218 Views

Last post by mamorani
Sat Mar 13, 2021 11:22 pm
Simulator is only supported on Linux. MATLAB and target HDL simulator must run on the same platform

Last post by mamorani « Sat Mar 13, 2021 11:21 pm

by mamorani » Sat Mar 13, 2021 11:21 pm

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202 Views

Last post by mamorani
Sat Mar 13, 2021 11:21 pm
SystemVerilog DPI testbench generation failed for model

Last post by mamorani « Sat Mar 13, 2021 11:21 pm

by mamorani » Sat Mar 13, 2021 11:21 pm

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206 Views

Last post by mamorani
Sat Mar 13, 2021 11:21 pm
HDL code coverage is only supported with ModelSim and Incisive,no code coverage flags will be generated.

Last post by mamorani « Sat Mar 13, 2021 11:21 pm

by mamorani » Sat Mar 13, 2021 11:21 pm

0 Replies

201 Views

Last post by mamorani
Sat Mar 13, 2021 11:21 pm
Word length of data type is greater than 64bit on port SystemVerilog DPI testbench only support word length up to 64bi

Last post by mamorani « Sat Mar 13, 2021 11:20 pm

by mamorani » Sat Mar 13, 2021 11:20 pm

0 Replies

197 Views

Last post by mamorani
Sat Mar 13, 2021 11:20 pm
SystemVerilog DPI testbench does not support multiple clocks. To avoid this error, change HDL code generation option "cl

Last post by mamorani « Sat Mar 13, 2021 11:20 pm

by mamorani » Sat Mar 13, 2021 11:20 pm

0 Replies

210 Views

Last post by mamorani
Sat Mar 13, 2021 11:20 pm
Found enumerated data type on port " . Enumerated data type is not supported for the input/output ports in SystemVerilog

Last post by mamorani « Sat Mar 13, 2021 11:19 pm

by mamorani » Sat Mar 13, 2021 11:19 pm

0 Replies

201 Views

Last post by mamorani
Sat Mar 13, 2021 11:19 pm
Found double precision data type on port Double precision data type is not supported for the input/output ports in Sys

Last post by mamorani « Sat Mar 13, 2021 11:18 pm

by mamorani » Sat Mar 13, 2021 11:18 pm

0 Replies

205 Views

Last post by mamorani
Sat Mar 13, 2021 11:18 pm
Preparing generated model for SystemVerilog DPI component generation

Last post by mamorani « Sat Mar 13, 2021 11:18 pm

by mamorani » Sat Mar 13, 2021 11:18 pm

0 Replies

207 Views

Last post by mamorani
Sat Mar 13, 2021 11:18 pm
Simulink Coder license is not available. SystemVerilog DPI testbench generation requires Simulink Coder

Last post by mamorani « Sat Mar 13, 2021 11:17 pm

by mamorani » Sat Mar 13, 2021 11:17 pm

0 Replies

202 Views

Last post by mamorani
Sat Mar 13, 2021 11:17 pm
does not exist. Demo must be published there to match content

Last post by mamorani « Sat Mar 13, 2021 11:16 pm

by mamorani » Sat Mar 13, 2021 11:16 pm

0 Replies

181 Views

Last post by mamorani
Sat Mar 13, 2021 11:16 pm
Remove folder "iseproject" from for proper publishing.

Last post by mamorani « Sat Mar 13, 2021 11:15 pm

by mamorani » Sat Mar 13, 2021 11:15 pm

0 Replies

178 Views

Last post by mamorani
Sat Mar 13, 2021 11:15 pm
Logging for passthrough signals is not supported for testbench generation

Last post by mamorani « Sat Mar 13, 2021 11:15 pm

by mamorani » Sat Mar 13, 2021 11:15 pm

0 Replies

201 Views

Last post by mamorani
Sat Mar 13, 2021 11:15 pm
Vector logging for test bench generation will execute in ''normal'' simulation mode

Last post by mamorani « Sat Mar 13, 2021 11:14 pm

by mamorani » Sat Mar 13, 2021 11:14 pm

0 Replies

227 Views

Last post by mamorani
Sat Mar 13, 2021 11:14 pm

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