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Scalar inputs are not supported. Use Multiply-Add block for this operation instead.

Last post by mamorani « Fri Mar 12, 2021 2:31 pm

by mamorani » Fri Mar 12, 2021 2:31 pm

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154 Views

Last post by mamorani
Fri Mar 12, 2021 2:31 pm
DSP mapping may not occur for inputs with differing fixed point types

Last post by mamorani « Fri Mar 12, 2021 2:31 pm

by mamorani » Fri Mar 12, 2021 2:31 pm

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139 Views

Last post by mamorani
Fri Mar 12, 2021 2:31 pm
DSP mapping may not occur for floating-point inputs.

Last post by mamorani « Fri Mar 12, 2021 2:30 pm

by mamorani » Fri Mar 12, 2021 2:30 pm

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143 Views

Last post by mamorani
Fri Mar 12, 2021 2:30 pm
The model has a ResetType setting that may be incompatible for DSP mapping in Altera boards. Set the ResetType model pro

Last post by mamorani « Fri Mar 12, 2021 2:30 pm

by mamorani » Fri Mar 12, 2021 2:30 pm

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154 Views

Last post by mamorani
Fri Mar 12, 2021 2:30 pm
Only one output port is supported in this block for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 2:30 pm

by mamorani » Fri Mar 12, 2021 2:30 pm

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141 Views

Last post by mamorani
Fri Mar 12, 2021 2:30 pm
Multicycle path generation is not supported in a design containing a Model Reference HDL implementation

Last post by mamorani « Fri Mar 12, 2021 2:29 pm

by mamorani » Fri Mar 12, 2021 2:29 pm

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157 Views

Last post by mamorani
Fri Mar 12, 2021 2:29 pm
Multiple clocks are specified along with MinimizeClockEnables, and HDL test bench generation has been requested. This is

Last post by mamorani « Fri Mar 12, 2021 2:29 pm

by mamorani » Fri Mar 12, 2021 2:29 pm

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174 Views

Last post by mamorani
Fri Mar 12, 2021 2:29 pm
Reference model can not inherit different rates for HDL code generation, but the one referred by the following Model blo

Last post by mamorani « Fri Mar 12, 2021 2:29 pm

by mamorani » Fri Mar 12, 2021 2:29 pm

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116 Views

Last post by mamorani
Fri Mar 12, 2021 2:29 pm
Protected model referenced at top-level DUT is unsupported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 2:28 pm

by mamorani » Fri Mar 12, 2021 2:28 pm

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130 Views

Last post by mamorani
Fri Mar 12, 2021 2:28 pm
Model blocks can not reference protected models for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 2:28 pm

by mamorani » Fri Mar 12, 2021 2:28 pm

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127 Views

Last post by mamorani
Fri Mar 12, 2021 2:28 pm
All Model blocks in a design hierarchy that refer to the same model must have identical HDL Block Properties. Blocks ''

Last post by mamorani « Fri Mar 12, 2021 2:27 pm

by mamorani » Fri Mar 12, 2021 2:27 pm

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132 Views

Last post by mamorani
Fri Mar 12, 2021 2:27 pm
IP Core Generation workflow targeting VHDL language is not supported in a design containing a Model Reference HDL implem

Last post by mamorani « Fri Mar 12, 2021 2:27 pm

by mamorani » Fri Mar 12, 2021 2:27 pm

0 Replies

133 Views

Last post by mamorani
Fri Mar 12, 2021 2:27 pm
Hierarchical Distributed Pipelining cannot be used in a design containing a ModelReference block. Hierarchical Distribut

Last post by mamorani « Fri Mar 12, 2021 2:27 pm

by mamorani » Fri Mar 12, 2021 2:27 pm

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128 Views

Last post by mamorani
Fri Mar 12, 2021 2:27 pm
Protected model cannot be created for a model having another protected model reference present in it

Last post by mamorani « Fri Mar 12, 2021 2:26 pm

by mamorani » Fri Mar 12, 2021 2:26 pm

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124 Views

Last post by mamorani
Fri Mar 12, 2021 2:26 pm
To generate HDL code for a model argument value in a Model block, the model argument value must be used as a Gain or Con

Last post by mamorani « Fri Mar 12, 2021 2:26 pm

by mamorani » Fri Mar 12, 2021 2:26 pm

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126 Views

Last post by mamorani
Fri Mar 12, 2021 2:26 pm
Model Argument value not supported. Only constant numerics or Workspace Model arguments can be used as generic values

Last post by mamorani « Fri Mar 12, 2021 2:26 pm

by mamorani » Fri Mar 12, 2021 2:26 pm

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117 Views

Last post by mamorani
Fri Mar 12, 2021 2:26 pm
Description text in the Model Properties of '' contains one or more non-ASCII characters. Non-ASCII characters in gener

Last post by mamorani « Fri Mar 12, 2021 2:25 pm

by mamorani » Fri Mar 12, 2021 2:25 pm

0 Replies

113 Views

Last post by mamorani
Fri Mar 12, 2021 2:25 pm
The min/max block does not support different input datatypes

Last post by mamorani « Fri Mar 12, 2021 2:25 pm

by mamorani » Fri Mar 12, 2021 2:25 pm

0 Replies

108 Views

Last post by mamorani
Fri Mar 12, 2021 2:25 pm
The Memory block is supported only if the ''Inherit Sample Time'' property is checked and neither the input nor the outp

Last post by mamorani « Fri Mar 12, 2021 2:24 pm

by mamorani » Fri Mar 12, 2021 2:24 pm

0 Replies

140 Views

Last post by mamorani
Fri Mar 12, 2021 2:24 pm
Port of model is a vector or matrix port, which must be scalarized when on a Model Reference interface for VHDL code ge

Last post by mamorani « Fri Mar 12, 2021 2:24 pm

by mamorani » Fri Mar 12, 2021 2:24 pm

0 Replies

111 Views

Last post by mamorani
Fri Mar 12, 2021 2:24 pm
Port ' of model is of Enumerated type, which is not supported on a Model Reference interface for VHDL code generation

Last post by mamorani « Fri Mar 12, 2021 2:24 pm

by mamorani » Fri Mar 12, 2021 2:24 pm

0 Replies

148 Views

Last post by mamorani
Fri Mar 12, 2021 2:24 pm
Testpoint signals with matrix types are unsupported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 2:23 pm

by mamorani » Fri Mar 12, 2021 2:23 pm

0 Replies

102 Views

Last post by mamorani
Fri Mar 12, 2021 2:23 pm
Math Function does not support complex data type.

Last post by mamorani « Fri Mar 12, 2021 2:23 pm

by mamorani » Fri Mar 12, 2021 2:23 pm

0 Replies

103 Views

Last post by mamorani
Fri Mar 12, 2021 2:23 pm
Masked subsystems are not supported as a non-top level DUT subsystem for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 2:23 pm

by mamorani » Fri Mar 12, 2021 2:23 pm

0 Replies

108 Views

Last post by mamorani
Fri Mar 12, 2021 2:23 pm
Logic signals must be implemented as boolean for HDL code generation. Select ''Implement logic signals as Boolean data (

Last post by mamorani « Fri Mar 12, 2021 1:47 pm

by mamorani » Fri Mar 12, 2021 1:47 pm

0 Replies

139 Views

Last post by mamorani
Fri Mar 12, 2021 1:47 pm

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