Vector port is not currently supported for FPGA-in-the-Loop. Set as "on" or "DUTLevel" in task , and then re-generate code
hdldialog
Vector port is not currently supported for FPGA-in-the-Loop. Set as "on" or "DUTLevel" in task , and then re-generate
Who is online
Users browsing this forum: No registered users and 10 guests