Vector port is not currently supported for FPGA-in-the-Loop. Set as "on" or "DUTLevel" in task , and then re-generate

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mamorani
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Vector port is not currently supported for FPGA-in-the-Loop. Set as "on" or "DUTLevel" in task , and then re-generate

Post by mamorani »

Vector port is not currently supported for FPGA-in-the-Loop. Set as "on" or "DUTLevel" in task , and then re-generate code


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