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Maximum word length for read data is but desired word length is

Last post by mamorani « Fri Mar 12, 2021 10:01 pm

by mamorani » Fri Mar 12, 2021 10:01 pm

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327 Views

Last post by mamorani
Fri Mar 12, 2021 10:01 pm
Data has elements but port expects data with elements.

Last post by mamorani « Fri Mar 12, 2021 10:01 pm

by mamorani » Fri Mar 12, 2021 10:01 pm

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Last post by mamorani
Fri Mar 12, 2021 10:01 pm
is not an AXI4-Stream interface, so cannot be used for streaming commands

Last post by mamorani « Fri Mar 12, 2021 10:01 pm

by mamorani » Fri Mar 12, 2021 10:01 pm

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276 Views

Last post by mamorani
Fri Mar 12, 2021 10:01 pm
No AXI4 Slave interfaces have an address space containing address

Last post by mamorani « Fri Mar 12, 2021 10:00 pm

by mamorani » Fri Mar 12, 2021 10:00 pm

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Last post by mamorani
Fri Mar 12, 2021 10:00 pm
Interfaces are AXI4-Stream interfaces. If multiple AXI4-Stream interfaces exist, you must specify an InterfaceID

Last post by mamorani « Fri Mar 12, 2021 10:00 pm

by mamorani » Fri Mar 12, 2021 10:00 pm

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339 Views

Last post by mamorani
Fri Mar 12, 2021 10:00 pm
Write is disabled but a write driver was specified.

Last post by mamorani « Fri Mar 12, 2021 9:59 pm

by mamorani » Fri Mar 12, 2021 9:59 pm

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227 Views

Last post by mamorani
Fri Mar 12, 2021 9:59 pm
An input port is already mapped to interface Multiple input ports cannot be mapped to AXI4-Stream interfaces

Last post by mamorani « Fri Mar 12, 2021 9:59 pm

by mamorani » Fri Mar 12, 2021 9:59 pm

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249 Views

Last post by mamorani
Fri Mar 12, 2021 9:59 pm
Port must be specified as an "hdlcoder.DUTPort" object

Last post by mamorani « Fri Mar 12, 2021 9:58 pm

by mamorani » Fri Mar 12, 2021 9:58 pm

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258 Views

Last post by mamorani
Fri Mar 12, 2021 9:58 pm
Port data type must be specified as the name of a built-in MATLAB numeric type or as a numerictype object

Last post by mamorani « Fri Mar 12, 2021 9:58 pm

by mamorani » Fri Mar 12, 2021 9:58 pm

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229 Views

Last post by mamorani
Fri Mar 12, 2021 9:58 pm
Output data type must be specified as the name of a built-in MATLAB numeric type or as a numerictype object

Last post by mamorani « Fri Mar 12, 2021 9:58 pm

by mamorani » Fri Mar 12, 2021 9:58 pm

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212 Views

Last post by mamorani
Fri Mar 12, 2021 9:58 pm
IP address must be specified as a string or character array.

Last post by mamorani « Fri Mar 12, 2021 9:57 pm

by mamorani » Fri Mar 12, 2021 9:57 pm

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246 Views

Last post by mamorani
Fri Mar 12, 2021 9:57 pm
is not the name of any interface. The names of the existing interfaces are

Last post by mamorani « Fri Mar 12, 2021 9:57 pm

by mamorani » Fri Mar 12, 2021 9:57 pm

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244 Views

Last post by mamorani
Fri Mar 12, 2021 9:57 pm
Port dimension does not align with expected frame size Port dimension must be specified as one of the following

Last post by mamorani « Fri Mar 12, 2021 9:57 pm

by mamorani » Fri Mar 12, 2021 9:57 pm

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236 Views

Last post by mamorani
Fri Mar 12, 2021 9:57 pm
Address space defined by base address and address range is outside maximum allowable address space. The maximum allowabl

Last post by mamorani « Fri Mar 12, 2021 9:55 pm

by mamorani » Fri Mar 12, 2021 9:55 pm

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219 Views

Last post by mamorani
Fri Mar 12, 2021 9:55 pm
Address provided with incorrect format. Address must either be specified as a numeric value such as 0x100, or as a strin

Last post by mamorani « Fri Mar 12, 2021 9:54 pm

by mamorani » Fri Mar 12, 2021 9:54 pm

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238 Views

Last post by mamorani
Fri Mar 12, 2021 9:54 pm
HDL Verifier hardware support package is required to use FPGA Data Capture Interface. Installation HDL Hardware Support

Last post by mamorani « Fri Mar 12, 2021 9:53 pm

by mamorani » Fri Mar 12, 2021 9:53 pm

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275 Views

Last post by mamorani
Fri Mar 12, 2021 9:53 pm
HDL Verifier license is required to use FPGA Data Capture interface

Last post by mamorani « Fri Mar 12, 2021 9:53 pm

by mamorani » Fri Mar 12, 2021 9:53 pm

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238 Views

Last post by mamorani
Fri Mar 12, 2021 9:53 pm
The HDL Coder setting "No-reset registers initialization" is set to "Generate an external script". This might cause mism

Last post by mamorani « Fri Mar 12, 2021 9:52 pm

by mamorani » Fri Mar 12, 2021 9:52 pm

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239 Views

Last post by mamorani
Fri Mar 12, 2021 9:52 pm
change HDL setting "No-reset registers initialization" to "Generate initialization inside module"

Last post by mamorani « Fri Mar 12, 2021 9:52 pm

by mamorani » Fri Mar 12, 2021 9:52 pm

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272 Views

Last post by mamorani
Fri Mar 12, 2021 9:52 pm
turn off HDL setting "Minimize global reset"

Last post by mamorani « Fri Mar 12, 2021 9:48 pm

by mamorani » Fri Mar 12, 2021 9:48 pm

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289 Views

Last post by mamorani
Fri Mar 12, 2021 9:48 pm
The HDL Coder setting "Minimize global resets" is enabled. This might cause either of the following results:\n 1. Failur

Last post by mamorani « Fri Mar 12, 2021 9:48 pm

by mamorani » Fri Mar 12, 2021 9:48 pm

0 Replies

264 Views

Last post by mamorani
Fri Mar 12, 2021 9:48 pm
Change model setting "SolverMode" to "SingleTasking".

Last post by mamorani « Fri Mar 12, 2021 9:47 pm

by mamorani » Fri Mar 12, 2021 9:47 pm

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251 Views

Last post by mamorani
Fri Mar 12, 2021 9:47 pm
FPGA-in-the-Loop test bench generation requires a solver in single tasking mode. Please click the following link to chan

Last post by mamorani « Fri Mar 12, 2021 9:47 pm

by mamorani » Fri Mar 12, 2021 9:47 pm

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218 Views

Last post by mamorani
Fri Mar 12, 2021 9:47 pm
Removing work directory as it is out of date.

Last post by mamorani « Fri Mar 12, 2021 9:46 pm

by mamorani » Fri Mar 12, 2021 9:46 pm

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208 Views

Last post by mamorani
Fri Mar 12, 2021 9:46 pm
Menu selection ''Export to script'' does not support the workflow '. Please select from ''IP Core Generation'', ''Gener

Last post by mamorani « Fri Mar 12, 2021 9:46 pm

by mamorani » Fri Mar 12, 2021 9:46 pm

0 Replies

248 Views

Last post by mamorani
Fri Mar 12, 2021 9:46 pm

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