The HDL Coder setting "Minimize global resets" is enabled. This might cause either of the following results:\n 1. Failur

[mamorani]

The HDL Coder setting "Minimize global resets" is enabled. This might cause either of the following results:\n 1. Failure to generate FPGA-in-the-Loop test bench.\n 2. Mismatches in FPGA-in-the-Loop test bench simulation results if there are no-reset registers with none-zero initial values.\n To avoid such simulation mismatches or test bench generation failures

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