Generate FPGA programming file for USRP(R) board. The FPGA project is generated first. Then syntax checking is performed

[mamorani]

Generate FPGA programming file for USRP(R) board. The FPGA project is generated first. Then syntax checking is performed on the HDL code. If no error was found in FPGA project generation and syntax checking, FPGA programming file generation process will start in an external command-line window

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