In order to work with Xilinx System Generator for DSP, clock and clock enable must be named as "clk" and "ce".

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In order to work with Xilinx System Generator for DSP, clock and clock enable must be named as "clk" and "ce".

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In order to work with Xilinx System Generator for DSP, clock and clock enable must be named as "clk" and "ce".

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