Identifiers and names should follow recommended naming convention (1.A.A.2), and keywords in Verilog-HDL(IEEE1364), Syst

Post Reply
mamorani
Posts: 8800
Joined: Thu Feb 25, 2021 6:50 pm
Contact:
Contact mamorani

Identifiers and names should follow recommended naming convention (1.A.A.2), and keywords in Verilog-HDL(IEEE1364), Syst

Post by mamorani »

Identifiers and names should follow recommended naming convention (1.A.A.2), and keywords in Verilog-HDL(IEEE1364), SystemVerilog(v3.1a), and keywords in VHDL(IEEE1076.X) must not be used
Standard
Top
Post Reply

Return to “Signal Processing”

Who is online

Users browsing this forum: No registered users and 11 guests