A resettable timing controller is not supported with FPGA-in-the-loop. To correct this issue, run ''hdlset_param( ''Tim

Post Reply
mamorani
Posts: 8800
Joined: Thu Feb 25, 2021 6:50 pm
Contact:
Contact mamorani

A resettable timing controller is not supported with FPGA-in-the-loop. To correct this issue, run ''hdlset_param( ''Tim

Post by mamorani »

A resettable timing controller is not supported with FPGA-in-the-loop. To correct this issue, run ''hdlset_param( ''TimingControllerArch'', ''default'')'

workflow
Top
Post Reply

Return to “Signal Processing”

Who is online

Users browsing this forum: No registered users and 18 guests