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Please select "Target Platform" of IP Core Generation Workflow before change this setting.

Last post by mamorani « Sat Mar 13, 2021 8:49 pm

by mamorani » Sat Mar 13, 2021 8:49 pm

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Last post by mamorani
Sat Mar 13, 2021 8:49 pm
This function should not be used with Generic IP Core platform, please select a non-generic target platform

Last post by mamorani « Sat Mar 13, 2021 8:48 pm

by mamorani » Sat Mar 13, 2021 8:48 pm

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261 Views

Last post by mamorani
Sat Mar 13, 2021 8:48 pm
Only consecutive bit range input is supported currently, for example: [LSB:MSB].

Last post by mamorani « Sat Mar 13, 2021 8:48 pm

by mamorani » Sat Mar 13, 2021 8:48 pm

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Last post by mamorani
Sat Mar 13, 2021 8:48 pm
must be turned on when AXI4 slave is mapped or when ProcessorFPGASynchronization mode is Coprocessing mode, is changed

Last post by mamorani « Sat Mar 13, 2021 8:48 pm

by mamorani » Sat Mar 13, 2021 8:48 pm

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Last post by mamorani
Sat Mar 13, 2021 8:48 pm
must be turned on for without AXI4 slave interface is not supported.

Last post by mamorani « Sat Mar 13, 2021 8:47 pm

by mamorani » Sat Mar 13, 2021 8:47 pm

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253 Views

Last post by mamorani
Sat Mar 13, 2021 8:47 pm
No reference designs exist for selected target platform . To use this target platform, please register a reference desi

Last post by mamorani « Sat Mar 13, 2021 8:46 pm

by mamorani » Sat Mar 13, 2021 8:46 pm

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265 Views

Last post by mamorani
Sat Mar 13, 2021 8:46 pm
Target synthesis tool project file ' does not exist.\nPlease check current working directory.

Last post by mamorani « Sat Mar 13, 2021 8:45 pm

by mamorani » Sat Mar 13, 2021 8:45 pm

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301 Views

Last post by mamorani
Sat Mar 13, 2021 8:45 pm
At least one subsystem outport need to be assigned with Interface

Last post by mamorani « Sat Mar 13, 2021 8:45 pm

by mamorani » Sat Mar 13, 2021 8:45 pm

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437 Views

Last post by mamorani
Sat Mar 13, 2021 8:45 pm
Unable to find bitstream file Check that the bitstream file exists.

Last post by mamorani « Sat Mar 13, 2021 8:45 pm

by mamorani » Sat Mar 13, 2021 8:45 pm

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327 Views

Last post by mamorani
Sat Mar 13, 2021 8:45 pm
Downstream Integration: Synthesis tool is not available on system path. Please add it to system path

Last post by mamorani « Sat Mar 13, 2021 8:43 pm

by mamorani » Sat Mar 13, 2021 8:43 pm

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269 Views

Last post by mamorani
Sat Mar 13, 2021 8:43 pm
Unable to get device data from synthesis tool, please provide device_list.xml file in downstream tool plug-in

Last post by mamorani « Sat Mar 13, 2021 8:43 pm

by mamorani » Sat Mar 13, 2021 8:43 pm

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290 Views

Last post by mamorani
Sat Mar 13, 2021 8:43 pm
FPGA top level wrapper generation require successful HDL code generation

Last post by mamorani « Sat Mar 13, 2021 8:43 pm

by mamorani » Sat Mar 13, 2021 8:43 pm

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322 Views

Last post by mamorani
Sat Mar 13, 2021 8:43 pm
VHDL code generation for model references is not supported for Microsemi Libero SoC.

Last post by mamorani « Sat Mar 13, 2021 8:43 pm

by mamorani » Sat Mar 13, 2021 8:43 pm

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333 Views

Last post by mamorani
Sat Mar 13, 2021 8:43 pm
Invalid Simulink Real-Time IO block path is specified in board plugin

Last post by mamorani « Sat Mar 13, 2021 8:42 pm

by mamorani » Sat Mar 13, 2021 8:42 pm

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301 Views

Last post by mamorani
Sat Mar 13, 2021 8:42 pm
ResetFPGAPin is not specified for constrain generation

Last post by mamorani « Sat Mar 13, 2021 8:42 pm

by mamorani » Sat Mar 13, 2021 8:42 pm

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299 Views

Last post by mamorani
Sat Mar 13, 2021 8:42 pm
Coprocessing mode requires all input and output ports uses the same sample rate, please check the sample rate for port

Last post by mamorani « Sat Mar 13, 2021 8:41 pm

by mamorani » Sat Mar 13, 2021 8:41 pm

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275 Views

Last post by mamorani
Sat Mar 13, 2021 8:41 pm
Mismatch on the port data type dimension of the input and output data port

Last post by mamorani « Sat Mar 13, 2021 8:41 pm

by mamorani » Sat Mar 13, 2021 8:41 pm

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309 Views

Last post by mamorani
Sat Mar 13, 2021 8:41 pm
Using interface with Ready port unassigned is not supported when "Minimize clock enables" is in effect, or when top-leve

Last post by mamorani « Sat Mar 13, 2021 8:40 pm

by mamorani » Sat Mar 13, 2021 8:40 pm

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269 Views

Last post by mamorani
Sat Mar 13, 2021 8:40 pm
Co-processing mode is not supported when "Minimize clock enables" is in effect, or when top-level HDL code contains cloc

Last post by mamorani « Sat Mar 13, 2021 8:40 pm

by mamorani » Sat Mar 13, 2021 8:40 pm

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345 Views

Last post by mamorani
Sat Mar 13, 2021 8:40 pm
Long project path can cause errors in the synthesis tool. Consider reducing the length of the path to ,number,intege

Last post by mamorani « Sat Mar 13, 2021 8:39 pm

by mamorani » Sat Mar 13, 2021 8:39 pm

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281 Views

Last post by mamorani
Sat Mar 13, 2021 8:39 pm
Unable to calculate synthesis tool version number. \nPlease make sure command is available and executable. \nSynthesis t

Last post by mamorani « Sat Mar 13, 2021 8:39 pm

by mamorani » Sat Mar 13, 2021 8:39 pm

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339 Views

Last post by mamorani
Sat Mar 13, 2021 8:39 pm
Downstream Integration: Invalid Stage ID when showing current status.

Last post by mamorani « Sat Mar 13, 2021 8:38 pm

by mamorani » Sat Mar 13, 2021 8:38 pm

0 Replies

281 Views

Last post by mamorani
Sat Mar 13, 2021 8:38 pm
Source file does not exist, please check current working directory

Last post by mamorani « Sat Mar 13, 2021 8:38 pm

by mamorani » Sat Mar 13, 2021 8:38 pm

0 Replies

385 Views

Last post by mamorani
Sat Mar 13, 2021 8:38 pm
Downstream Integration: Project directory cannot be empty.

Last post by mamorani « Sat Mar 13, 2021 8:38 pm

by mamorani » Sat Mar 13, 2021 8:38 pm

0 Replies

265 Views

Last post by mamorani
Sat Mar 13, 2021 8:38 pm
Coprocessing mode does not support sample rate on port

Last post by mamorani « Sat Mar 13, 2021 8:37 pm

by mamorani » Sat Mar 13, 2021 8:37 pm

0 Replies

324 Views

Last post by mamorani
Sat Mar 13, 2021 8:37 pm

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