Signal Processing

New Topic

3049 topics

Page 3 of 122
- Jump to page:
Previous
1
2
3
4
5
…
122
Next

Topics

Replies

Views

Last post

SETS must be passed as a cell-array of handles to objects

Last post by mamorani « Sun Mar 14, 2021 9:08 pm

by mamorani » Sun Mar 14, 2021 9:08 pm

0 Replies

632 Views

Last post by mamorani
Sun Mar 14, 2021 9:08 pm
NAMES must be a non-empty cell-array of character vectors

Last post by mamorani « Sun Mar 14, 2021 9:06 pm

by mamorani » Sun Mar 14, 2021 9:06 pm

0 Replies

663 Views

Last post by mamorani
Sun Mar 14, 2021 9:06 pm
The generated simulation scripts might not work.Using scripts to initialize registers is only supported by ''Mentor Grap

Last post by mamorani « Sun Mar 14, 2021 9:03 pm

by mamorani » Sun Mar 14, 2021 9:03 pm

0 Replies

682 Views

Last post by mamorani
Sun Mar 14, 2021 9:03 pm
simulator script generation is only supported for ''Mentor Graphics ModelSim'' simulation tool.Please change the simulat

Last post by mamorani « Sun Mar 14, 2021 9:02 pm

by mamorani » Sun Mar 14, 2021 9:02 pm

0 Replies

653 Views

Last post by mamorani
Sun Mar 14, 2021 9:02 pm
is used by simulation and requires reset be asserted for at least 100 ns. However, the current test bench settings only

Last post by mamorani « Sun Mar 14, 2021 9:02 pm

by mamorani » Sun Mar 14, 2021 9:02 pm

0 Replies

633 Views

Last post by mamorani
Sun Mar 14, 2021 9:02 pm
vcom" or "vlog" is required to compile target-specific codes, while the compile command for VHDL or Verilog seems using

Last post by mamorani « Sun Mar 14, 2021 8:58 pm

by mamorani » Sun Mar 14, 2021 8:58 pm

0 Replies

732 Views

Last post by mamorani
Sun Mar 14, 2021 8:58 pm
Cannot generate test bench for this model. The model doesn''t have any inputs or outputs

Last post by mamorani « Sun Mar 14, 2021 8:58 pm

by mamorani » Sun Mar 14, 2021 8:58 pm

0 Replies

671 Views

Last post by mamorani
Sun Mar 14, 2021 8:58 pm
Cannot generate testbench without input and output data

Last post by mamorani « Sun Mar 14, 2021 8:58 pm

by mamorani » Sun Mar 14, 2021 8:58 pm

0 Replies

729 Views

Last post by mamorani
Sun Mar 14, 2021 8:58 pm
Data-type ' is unsupported for HDL code generation. If Xilinx System Generator Subsystem is used, make sure it is not t

Last post by mamorani « Sun Mar 14, 2021 8:57 pm

by mamorani » Sun Mar 14, 2021 8:57 pm

0 Replies

735 Views

Last post by mamorani
Sun Mar 14, 2021 8:57 pm
Input data interval must be greater than or equal to

Last post by mamorani « Sun Mar 14, 2021 8:57 pm

by mamorani » Sun Mar 14, 2021 8:57 pm

0 Replies

591 Views

Last post by mamorani
Sun Mar 14, 2021 8:57 pm
SynthesisToolDeviceName not specified. Using default value, SynthesisToolDeviceName for

Last post by mamorani « Sun Mar 14, 2021 8:56 pm

by mamorani » Sun Mar 14, 2021 8:56 pm

0 Replies

642 Views

Last post by mamorani
Sun Mar 14, 2021 8:56 pm
Family or Speed grade not characterized. Using default values, SynthesisToolChipFamily and SynthesisToolSpeedValue

Last post by mamorani « Sun Mar 14, 2021 8:56 pm

by mamorani » Sun Mar 14, 2021 8:56 pm

0 Replies

621 Views

Last post by mamorani
Sun Mar 14, 2021 8:56 pm
Family not characterized. Using default value, SynthesisToolChipFamily and SynthesisToolSpeedValue for

Last post by mamorani « Sun Mar 14, 2021 8:55 pm

by mamorani » Sun Mar 14, 2021 8:55 pm

0 Replies

713 Views

Last post by mamorani
Sun Mar 14, 2021 8:55 pm
SynthesisToolSpeedValue not characterized for Family Using default value, SynthesisToolSpeedValue= , for critical path

Last post by mamorani « Sun Mar 14, 2021 8:55 pm

by mamorani » Sun Mar 14, 2021 8:55 pm

0 Replies

779 Views

Last post by mamorani
Sun Mar 14, 2021 8:55 pm
SynthesisToolDeviceName not specified. Using default value, SynthesisToolDeviceName for critical path estimation

Last post by mamorani « Sun Mar 14, 2021 8:53 pm

by mamorani » Sun Mar 14, 2021 8:53 pm

0 Replies

606 Views

Last post by mamorani
Sun Mar 14, 2021 8:53 pm
SynthesisToolDeviceName not characterized for Family . Using default value, SynthesisToolDeviceName for critical pat

Last post by mamorani « Sun Mar 14, 2021 8:53 pm

by mamorani » Sun Mar 14, 2021 8:53 pm

0 Replies

650 Views

Last post by mamorani
Sun Mar 14, 2021 8:53 pm
The model contains multiple rates, which are either explicitly designed or introduced by optimizations. Critical Path Es

Last post by mamorani « Sun Mar 14, 2021 8:52 pm

by mamorani » Sun Mar 14, 2021 8:52 pm

0 Replies

662 Views

Last post by mamorani
Sun Mar 14, 2021 8:52 pm
SynthesisToolChipFamily or SynthesisToolSpeedValue not specified. Using default values, SynthesisToolChipFamily=virtex7

Last post by mamorani « Sun Mar 14, 2021 8:52 pm

by mamorani » Sun Mar 14, 2021 8:52 pm

0 Replies

672 Views

Last post by mamorani
Sun Mar 14, 2021 8:52 pm
SynthesisToolChipFamily not specified. Using default value, SynthesisToolChipFamily=virtex7, for critical path estimatio

Last post by mamorani « Sun Mar 14, 2021 8:52 pm

by mamorani » Sun Mar 14, 2021 8:52 pm

0 Replies

661 Views

Last post by mamorani
Sun Mar 14, 2021 8:52 pm
SynthesisToolChipFamily not specified. Using default value, SynthesisToolChipFamily=virtex7, for critical path estimatio

Last post by mamorani « Sun Mar 14, 2021 8:51 pm

by mamorani » Sun Mar 14, 2021 8:51 pm

0 Replies

822 Views

Last post by mamorani
Sun Mar 14, 2021 8:51 pm
Family not characterized. Using default value, SynthesisToolChipFamily for critical path estimation.

Last post by mamorani « Sun Mar 14, 2021 8:50 pm

by mamorani » Sun Mar 14, 2021 8:50 pm

0 Replies

609 Views

Last post by mamorani
Sun Mar 14, 2021 8:50 pm
PV pair is required if any parameter is passed to the constructor

Last post by mamorani « Sun Mar 14, 2021 8:49 pm

by mamorani » Sun Mar 14, 2021 8:49 pm

0 Replies

759 Views

Last post by mamorani
Sun Mar 14, 2021 8:49 pm
HDL Optimized implementation of sine function in fixed point using a lookup table approach that exploits quarter wave sy

Last post by mamorani « Sun Mar 14, 2021 8:49 pm

by mamorani » Sun Mar 14, 2021 8:49 pm

0 Replies

652 Views

Last post by mamorani
Sun Mar 14, 2021 8:49 pm
Cannot set property which maybe non-existent, or deprecated. Exception '' with message '

Last post by mamorani « Sun Mar 14, 2021 8:47 pm

by mamorani » Sun Mar 14, 2021 8:47 pm

0 Replies

619 Views

Last post by mamorani
Sun Mar 14, 2021 8:47 pm
HDL test bench generation for multirate models requires a fixed step, discrete solver in single tasking mode. In the Sol

Last post by mamorani « Sun Mar 14, 2021 8:47 pm

by mamorani » Sun Mar 14, 2021 8:47 pm

0 Replies

637 Views

Last post by mamorani
Sun Mar 14, 2021 8:47 pm

New Topic

3049 topics

Page 3 of 122
- Jump to page:
Previous
1
2
3
4
5
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 7 guests

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum