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The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays

Last post by mamorani « Wed Mar 10, 2021 9:08 pm

by mamorani » Wed Mar 10, 2021 9:08 pm

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Last post by mamorani
Wed Mar 10, 2021 9:08 pm
The delay balancing feature has automatically inserted matching delays for compensation

Last post by mamorani « Wed Mar 10, 2021 9:08 pm

by mamorani » Wed Mar 10, 2021 9:08 pm

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Last post by mamorani
Wed Mar 10, 2021 9:08 pm
The code generation and optimization options you have chosen have introduced additional pipeline delays

Last post by mamorani « Wed Mar 10, 2021 9:07 pm

by mamorani » Wed Mar 10, 2021 9:07 pm

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Last post by mamorani
Wed Mar 10, 2021 9:07 pm
Generating Xilinx(R) CORE Generator(TM) block: for latency of

Last post by mamorani « Wed Mar 10, 2021 9:07 pm

by mamorani » Wed Mar 10, 2021 9:07 pm

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Last post by mamorani
Wed Mar 10, 2021 9:07 pm
Clock-rate pipelining was applied on signals connected to the DUT's output ports. The DUT output port values are therefo

Last post by mamorani « Wed Mar 10, 2021 9:07 pm

by mamorani » Wed Mar 10, 2021 9:07 pm

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Last post by mamorani
Wed Mar 10, 2021 9:07 pm
Info: The closest available output frequency of the clock module is MHz, which is different from your specified FPGA sy

Last post by mamorani « Wed Mar 10, 2021 9:06 pm

by mamorani » Wed Mar 10, 2021 9:06 pm

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Last post by mamorani
Wed Mar 10, 2021 9:06 pm
To clear highlighting, click the following MATLAB script:

Last post by mamorani « Wed Mar 10, 2021 9:05 pm

by mamorani » Wed Mar 10, 2021 9:05 pm

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148 Views

Last post by mamorani
Wed Mar 10, 2021 9:05 pm
Info: the clock module params are clk0_multiply_by = ; clk0_divide_by =

Last post by mamorani « Wed Mar 10, 2021 9:04 pm

by mamorani » Wed Mar 10, 2021 9:04 pm

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Last post by mamorani
Wed Mar 10, 2021 9:04 pm
All logic inside the DUT was detected to be redundant by HDL Coder. Consider connecting output ports to the design in

Last post by mamorani « Wed Mar 10, 2021 9:03 pm

by mamorani » Wed Mar 10, 2021 9:03 pm

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Last post by mamorani
Wed Mar 10, 2021 9:03 pm
does not contain a unique System Generator block

Last post by mamorani « Wed Mar 10, 2021 9:02 pm

by mamorani » Wed Mar 10, 2021 9:02 pm

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153 Views

Last post by mamorani
Wed Mar 10, 2021 9:02 pm
HDL simulator not ready for minutes -- aborting

Last post by mamorani « Wed Mar 10, 2021 9:01 pm

by mamorani » Wed Mar 10, 2021 9:01 pm

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Last post by mamorani
Wed Mar 10, 2021 9:01 pm
Cannot find top-level model path from input path

Last post by mamorani « Wed Mar 10, 2021 9:01 pm

by mamorani » Wed Mar 10, 2021 9:01 pm

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175 Views

Last post by mamorani
Wed Mar 10, 2021 9:01 pm
More than one DSP Builder Clock blocks found in the model

Last post by mamorani « Wed Mar 10, 2021 9:00 pm

by mamorani » Wed Mar 10, 2021 9:00 pm

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179 Views

Last post by mamorani
Wed Mar 10, 2021 9:00 pm
"Goto" and "From" wiring is not supported when block exists in the same level of subsystem hierarchy. Please wrap this

Last post by mamorani « Wed Mar 10, 2021 8:46 pm

by mamorani » Wed Mar 10, 2021 8:46 pm

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Last post by mamorani
Wed Mar 10, 2021 8:46 pm
Warning: Unable to find matching "From" block for "Goto" block inside of the DUT. This "Goto" block will be ignored dur

Last post by mamorani « Wed Mar 10, 2021 8:45 pm

by mamorani » Wed Mar 10, 2021 8:45 pm

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185 Views

Last post by mamorani
Wed Mar 10, 2021 8:45 pm
Goto" and "From" wiring do not support multiple instantiation of network

Last post by mamorani « Wed Mar 10, 2021 8:44 pm

by mamorani » Wed Mar 10, 2021 8:44 pm

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149 Views

Last post by mamorani
Wed Mar 10, 2021 8:44 pm
Unable to find matching "Goto" block for "From" block inside of the DUT. HDL code generation requires matching "Goto" b

Last post by mamorani « Wed Mar 10, 2021 8:44 pm

by mamorani » Wed Mar 10, 2021 8:44 pm

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154 Views

Last post by mamorani
Wed Mar 10, 2021 8:44 pm
License for ''HDL Verifier(TM)'' is not available or installation is incomplete

Last post by mamorani « Wed Mar 10, 2021 8:40 pm

by mamorani » Wed Mar 10, 2021 8:40 pm

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194 Views

Last post by mamorani
Wed Mar 10, 2021 8:40 pm
Failed to checkout HDL Verifier license for ''FPGA-in-the-Loop'' workflow

Last post by mamorani « Wed Mar 10, 2021 8:40 pm

by mamorani » Wed Mar 10, 2021 8:40 pm

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184 Views

Last post by mamorani
Wed Mar 10, 2021 8:40 pm
invalid min sample time ( found on the cosimulation interface:

Last post by mamorani « Wed Mar 10, 2021 8:39 pm

by mamorani » Wed Mar 10, 2021 8:39 pm

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171 Views

Last post by mamorani
Wed Mar 10, 2021 8:39 pm
Testbench with DUT wrapper logic cannot be generated when DUT is a Model block. Try wrapping the block into a virtual su

Last post by mamorani « Wed Mar 10, 2021 8:38 pm

by mamorani » Wed Mar 10, 2021 8:38 pm

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161 Views

Last post by mamorani
Wed Mar 10, 2021 8:38 pm
Testbench with DUT wrapper logic is unsuccessful when DUT is an atomic subsystem. Try converting the DUT to a virtual su

Last post by mamorani « Wed Mar 10, 2021 8:38 pm

by mamorani » Wed Mar 10, 2021 8:38 pm

0 Replies

170 Views

Last post by mamorani
Wed Mar 10, 2021 8:38 pm
Variable-size signal is not supported for HDL code generation.

Last post by mamorani « Wed Mar 10, 2021 8:37 pm

by mamorani » Wed Mar 10, 2021 8:37 pm

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158 Views

Last post by mamorani
Wed Mar 10, 2021 8:37 pm
The Simulink simulation stop time has been changed since HDL code was generated. The updated stop time ' will be used i

Last post by mamorani « Wed Mar 10, 2021 8:36 pm

by mamorani » Wed Mar 10, 2021 8:36 pm

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187 Views

Last post by mamorani
Wed Mar 10, 2021 8:36 pm
Value of the model argument ' ' is not scalar. Model argument value must be scalar for HDL code generation

Last post by mamorani « Wed Mar 10, 2021 8:36 pm

by mamorani » Wed Mar 10, 2021 8:36 pm

0 Replies

161 Views

Last post by mamorani
Wed Mar 10, 2021 8:36 pm

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