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Internal Error: ''Message'' field in the return structure of validate function of class should be a character vector.

Last post by mamorani « Wed Mar 10, 2021 9:43 pm

by mamorani » Wed Mar 10, 2021 9:43 pm

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Last post by mamorani
Wed Mar 10, 2021 9:43 pm
Internal Error: Invalid Return argument from validate function of class

Last post by mamorani « Wed Mar 10, 2021 9:40 pm

by mamorani » Wed Mar 10, 2021 9:40 pm

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210 Views

Last post by mamorani
Wed Mar 10, 2021 9:40 pm
Error: Evaluation of elaborate function on class failed with the error message

Last post by mamorani « Wed Mar 10, 2021 9:38 pm

by mamorani » Wed Mar 10, 2021 9:38 pm

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176 Views

Last post by mamorani
Wed Mar 10, 2021 9:38 pm
Additional HDL synchronization latency of 1 sample added

Last post by mamorani « Wed Mar 10, 2021 9:31 pm

by mamorani » Wed Mar 10, 2021 9:31 pm

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195 Views

Last post by mamorani
Wed Mar 10, 2021 9:31 pm
Using the config set for model <a href="matlab:configset.showParameterGroup( 'HDL Code Generation'' </a> for HDL code g

Last post by mamorani « Wed Mar 10, 2021 9:29 pm

by mamorani » Wed Mar 10, 2021 9:29 pm

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190 Views

Last post by mamorani
Wed Mar 10, 2021 9:29 pm
Info: the DCM params are CLKFX_MULTIPLY = CLKFX_DIVIDE

Last post by mamorani « Wed Mar 10, 2021 9:28 pm

by mamorani » Wed Mar 10, 2021 9:28 pm

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198 Views

Last post by mamorani
Wed Mar 10, 2021 9:28 pm
HDL Code not generated. Skipping Project creation step

Last post by mamorani « Wed Mar 10, 2021 9:26 pm

by mamorani » Wed Mar 10, 2021 9:26 pm

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176 Views

Last post by mamorani
Wed Mar 10, 2021 9:26 pm
Skipping validation model generation because delay balancing failed

Last post by mamorani « Wed Mar 10, 2021 9:25 pm

by mamorani » Wed Mar 10, 2021 9:25 pm

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194 Views

Last post by mamorani
Wed Mar 10, 2021 9:25 pm
HDL Code not generated. Skipping Implementation step

Last post by mamorani « Wed Mar 10, 2021 9:24 pm

by mamorani » Wed Mar 10, 2021 9:24 pm

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190 Views

Last post by mamorani
Wed Mar 10, 2021 9:24 pm
MESSAGE: The design requires times faster clock with respect to the base rate

Last post by mamorani « Wed Mar 10, 2021 9:23 pm

by mamorani » Wed Mar 10, 2021 9:23 pm

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192 Views

Last post by mamorani
Wed Mar 10, 2021 9:23 pm
'WARNING: The design requires times faster clock with respect to the base rate = which\n\t\t\t is incompatible with th

Last post by mamorani « Wed Mar 10, 2021 9:22 pm

by mamorani » Wed Mar 10, 2021 9:22 pm

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199 Views

Last post by mamorani
Wed Mar 10, 2021 9:22 pm
HDL Coder option 'nativeFloatingPoint' is on. HDL code in NativeFloatingPoint mode will be generated.

Last post by mamorani « Wed Mar 10, 2021 9:20 pm

by mamorani » Wed Mar 10, 2021 9:20 pm

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197 Views

Last post by mamorani
Wed Mar 10, 2021 9:20 pm
HDL Coder option 'nativeFloatingPoint' is on. HDL code in NativeFloatingPoint mode will be generated.

Last post by mamorani « Wed Mar 10, 2021 9:19 pm

by mamorani » Wed Mar 10, 2021 9:19 pm

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194 Views

Last post by mamorani
Wed Mar 10, 2021 9:19 pm
This multi-rate design has a high delay balancing latency of cycles, which is undesirable for HDL Code generation. Plea

Last post by mamorani « Wed Mar 10, 2021 9:18 pm

by mamorani » Wed Mar 10, 2021 9:18 pm

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180 Views

Last post by mamorani
Wed Mar 10, 2021 9:18 pm
One or more blocks are inhibiting streaming and/or sharing optimizations. To highlight these blocks in your original mod

Last post by mamorani « Wed Mar 10, 2021 9:17 pm

by mamorani » Wed Mar 10, 2021 9:17 pm

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168 Views

Last post by mamorani
Wed Mar 10, 2021 9:17 pm
To highlight the critical paths identified by the distributed pipelining optimization, click the following MATLAB script

Last post by mamorani « Wed Mar 10, 2021 9:17 pm

by mamorani » Wed Mar 10, 2021 9:17 pm

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197 Views

Last post by mamorani
Wed Mar 10, 2021 9:17 pm
One or more feedback loops in the model are inhibiting optimizations. To highlight these loops in your model, click the

Last post by mamorani « Wed Mar 10, 2021 9:16 pm

by mamorani » Wed Mar 10, 2021 9:16 pm

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155 Views

Last post by mamorani
Wed Mar 10, 2021 9:16 pm
To highlight blocks that obstruct distributed pipelining, click the following MATLAB script:

Last post by mamorani « Wed Mar 10, 2021 9:16 pm

by mamorani » Wed Mar 10, 2021 9:16 pm

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170 Views

Last post by mamorani
Wed Mar 10, 2021 9:16 pm
Clock-rate pipelining results can be diagnosed by running this script

Last post by mamorani « Wed Mar 10, 2021 9:16 pm

by mamorani » Wed Mar 10, 2021 9:16 pm

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165 Views

Last post by mamorani
Wed Mar 10, 2021 9:16 pm
Generated static latency analysis report for the design

Last post by mamorani « Wed Mar 10, 2021 9:15 pm

by mamorani » Wed Mar 10, 2021 9:15 pm

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158 Views

Last post by mamorani
Wed Mar 10, 2021 9:15 pm
Blocks that are not characterized for Critical Path Estimation

Last post by mamorani « Wed Mar 10, 2021 9:14 pm

by mamorani » Wed Mar 10, 2021 9:14 pm

0 Replies

318 Views

Last post by mamorani
Wed Mar 10, 2021 9:14 pm
HDL model property ''GenerateModel'' must be set to ''on'' during HDL code generation in order to generate a testbench,

Last post by mamorani « Wed Mar 10, 2021 9:14 pm

by mamorani » Wed Mar 10, 2021 9:14 pm

0 Replies

178 Views

Last post by mamorani
Wed Mar 10, 2021 9:14 pm
HDL Testbench generation for '' completed with errors, warnings, and messages

Last post by mamorani « Wed Mar 10, 2021 9:13 pm

by mamorani » Wed Mar 10, 2021 9:13 pm

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151 Views

Last post by mamorani
Wed Mar 10, 2021 9:13 pm
Info: The output frequency of the clock module might be different from your specified FPGA system clock frequency.

Last post by mamorani « Wed Mar 10, 2021 9:11 pm

by mamorani » Wed Mar 10, 2021 9:11 pm

0 Replies

160 Views

Last post by mamorani
Wed Mar 10, 2021 9:11 pm
Note: Option ''Allow Direct Feedthrough'' has been set to ''on'' on

Last post by mamorani « Wed Mar 10, 2021 9:10 pm

by mamorani » Wed Mar 10, 2021 9:10 pm

0 Replies

167 Views

Last post by mamorani
Wed Mar 10, 2021 9:10 pm

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