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HDL code generation does not support arithmetic on enumerated types, a

Last post by mamorani « Wed Mar 10, 2021 10:38 pm

by mamorani » Wed Mar 10, 2021 10:38 pm

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Last post by mamorani
Wed Mar 10, 2021 10:38 pm
Enumerated name ' ' introduces conflicting values. Please use unique enum type name and enum value pairs for Verilog cod

Last post by mamorani « Wed Mar 10, 2021 10:38 pm

by mamorani » Wed Mar 10, 2021 10:38 pm

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255 Views

Last post by mamorani
Wed Mar 10, 2021 10:38 pm
Enumerated name conflicts with the signal name This can lead to non synthesizable code.

Last post by mamorani « Wed Mar 10, 2021 10:36 pm

by mamorani » Wed Mar 10, 2021 10:36 pm

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278 Views

Last post by mamorani
Wed Mar 10, 2021 10:36 pm
Enumerated name is present in types '' ' and . Use unique enum type names for HDL code generation

Last post by mamorani « Wed Mar 10, 2021 10:36 pm

by mamorani » Wed Mar 10, 2021 10:36 pm

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276 Views

Last post by mamorani
Wed Mar 10, 2021 10:36 pm
The enumeration type ' contains an element with the enumeration identifier ' which is either a language keyword, or is

Last post by mamorani « Wed Mar 10, 2021 10:35 pm

by mamorani » Wed Mar 10, 2021 10:35 pm

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215 Views

Last post by mamorani
Wed Mar 10, 2021 10:35 pm
Altera DSPBA subsystem entity causes name conflict. Please rename it

Last post by mamorani « Wed Mar 10, 2021 10:35 pm

by mamorani » Wed Mar 10, 2021 10:35 pm

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244 Views

Last post by mamorani
Wed Mar 10, 2021 10:35 pm
There are no models open to apply the control file

Last post by mamorani « Wed Mar 10, 2021 10:34 pm

by mamorani » Wed Mar 10, 2021 10:34 pm

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238 Views

Last post by mamorani
Wed Mar 10, 2021 10:34 pm
cannot be represented with the selected fraction length

Last post by mamorani « Wed Mar 10, 2021 10:33 pm

by mamorani » Wed Mar 10, 2021 10:33 pm

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236 Views

Last post by mamorani
Wed Mar 10, 2021 10:33 pm
There are no models open with the name ' to apply the control file

Last post by mamorani « Wed Mar 10, 2021 10:32 pm

by mamorani » Wed Mar 10, 2021 10:32 pm

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275 Views

Last post by mamorani
Wed Mar 10, 2021 10:32 pm
The periodic sample time is not allowed because the ratio ) of this sample time over the HDL DUT base rate is great

Last post by mamorani « Wed Mar 10, 2021 10:32 pm

by mamorani » Wed Mar 10, 2021 10:32 pm

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312 Views

Last post by mamorani
Wed Mar 10, 2021 10:32 pm
The following parameters are transient and cannot be set with hdlset_param:

Last post by mamorani « Wed Mar 10, 2021 10:31 pm

by mamorani » Wed Mar 10, 2021 10:31 pm

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254 Views

Last post by mamorani
Wed Mar 10, 2021 10:31 pm
Setting Simulink binary-point to maximum value of 1024; HDL results may not match

Last post by mamorani « Wed Mar 10, 2021 10:31 pm

by mamorani » Wed Mar 10, 2021 10:31 pm

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254 Views

Last post by mamorani
Wed Mar 10, 2021 10:31 pm
Cannot find required information -- please make sure the block is in a model, not a library

Last post by mamorani « Wed Mar 10, 2021 10:30 pm

by mamorani » Wed Mar 10, 2021 10:30 pm

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268 Views

Last post by mamorani
Wed Mar 10, 2021 10:30 pm
Invalid ''Architecture'' parameter specified for the block\nValid Architecture names are

Last post by mamorani « Wed Mar 10, 2021 10:29 pm

by mamorani » Wed Mar 10, 2021 10:29 pm

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273 Views

Last post by mamorani
Wed Mar 10, 2021 10:29 pm
Critical Path Estimation doesn't support Float/Double types. Run diagnostics script for details.

Last post by mamorani « Wed Mar 10, 2021 10:28 pm

by mamorani » Wed Mar 10, 2021 10:28 pm

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231 Views

Last post by mamorani
Wed Mar 10, 2021 10:28 pm
Model Reference as top-level subsystem is not support for traceability report generation

Last post by mamorani « Wed Mar 10, 2021 10:28 pm

by mamorani » Wed Mar 10, 2021 10:28 pm

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260 Views

Last post by mamorani
Wed Mar 10, 2021 10:28 pm
Floating Point Target IP generation failed with the error message

Last post by mamorani « Wed Mar 10, 2021 10:27 pm

by mamorani » Wed Mar 10, 2021 10:27 pm

0 Replies

247 Views

Last post by mamorani
Wed Mar 10, 2021 10:27 pm
Trigger as clock mode requires synchronization registers for each input data signal to a triggered subsystem. Subsystem

Last post by mamorani « Wed Mar 10, 2021 10:25 pm

by mamorani » Wed Mar 10, 2021 10:25 pm

0 Replies

226 Views

Last post by mamorani
Wed Mar 10, 2021 10:25 pm
The block contains unsupported struct expressions. HDL code generation cannot proceed because of the unsupported const

Last post by mamorani « Wed Mar 10, 2021 10:25 pm

by mamorani » Wed Mar 10, 2021 10:25 pm

0 Replies

210 Views

Last post by mamorani
Wed Mar 10, 2021 10:25 pm
Single or double data type found in HDL code at Floating point data types are not synthesizable

Last post by mamorani « Wed Mar 10, 2021 10:23 pm

by mamorani » Wed Mar 10, 2021 10:23 pm

0 Replies

257 Views

Last post by mamorani
Wed Mar 10, 2021 10:23 pm
Single or double data type found in HDL code, at Floating point data types are not synthesizable. To fix this problem,

Last post by mamorani « Wed Mar 10, 2021 10:23 pm

by mamorani » Wed Mar 10, 2021 10:23 pm

0 Replies

281 Views

Last post by mamorani
Wed Mar 10, 2021 10:23 pm
A transform or optimization has created RAM block inside a resettable subsystem. This is not supported

Last post by mamorani « Wed Mar 10, 2021 10:22 pm

by mamorani » Wed Mar 10, 2021 10:22 pm

0 Replies

253 Views

Last post by mamorani
Wed Mar 10, 2021 10:22 pm
When RAMArchitecture is set to WithoutClockEnable, the testbench InputDataInterval must be 2 or less

Last post by mamorani « Wed Mar 10, 2021 10:22 pm

by mamorani » Wed Mar 10, 2021 10:22 pm

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232 Views

Last post by mamorani
Wed Mar 10, 2021 10:22 pm
The FFT length must be a power of 2, in the range from 2^3 to 2^16. The block name is

Last post by mamorani « Wed Mar 10, 2021 10:21 pm

by mamorani » Wed Mar 10, 2021 10:21 pm

0 Replies

243 Views

Last post by mamorani
Wed Mar 10, 2021 10:21 pm
Internal error detected in code generation data. One possible cause is that the design has no output ports. This is not

Last post by mamorani « Wed Mar 10, 2021 10:20 pm

by mamorani » Wed Mar 10, 2021 10:20 pm

0 Replies

228 Views

Last post by mamorani
Wed Mar 10, 2021 10:20 pm

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