Signal Processing

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Skipping simulation of test bench since MATLAB test bench is not available

Last post by mamorani « Fri Mar 12, 2021 9:34 am

by mamorani » Fri Mar 12, 2021 9:34 am

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Last post by mamorani
Fri Mar 12, 2021 9:34 am
To manually run the generated test bench, execute the following commands in MATLAB

Last post by mamorani « Fri Mar 12, 2021 9:34 am

by mamorani » Fri Mar 12, 2021 9:34 am

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Last post by mamorani
Fri Mar 12, 2021 9:34 am
Checking compatibility with test bench generation

Last post by mamorani « Fri Mar 12, 2021 9:33 am

by mamorani » Fri Mar 12, 2021 9:33 am

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249 Views

Last post by mamorani
Fri Mar 12, 2021 9:33 am
The interface port ed to a Deserializer1D block with ValidIn port enabled, ValidOut disabled, and StartOut disabled.

Last post by mamorani « Fri Mar 12, 2021 9:33 am

by mamorani » Fri Mar 12, 2021 9:33 am

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224 Views

Last post by mamorani
Fri Mar 12, 2021 9:33 am
Serializer1D block output port is connected to a vector signal. The output of a Serializer1D block connected to an inte

Last post by mamorani « Fri Mar 12, 2021 9:21 am

by mamorani » Fri Mar 12, 2021 9:21 am

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228 Views

Last post by mamorani
Fri Mar 12, 2021 9:21 am
Interface mismatch at vector port For the Deserializer1D block connected to the port, enable ValidIn and StartOut a

Last post by mamorani « Fri Mar 12, 2021 9:19 am

by mamorani » Fri Mar 12, 2021 9:19 am

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269 Views

Last post by mamorani
Fri Mar 12, 2021 9:19 am
The interface port cannot be scalar. If one AXI4-Stream interface port is connected to a vector signal, all other AXI

Last post by mamorani « Fri Mar 12, 2021 9:18 am

by mamorani » Fri Mar 12, 2021 9:18 am

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261 Views

Last post by mamorani
Fri Mar 12, 2021 9:18 am
Rate mismatch at port Serializer1D block outputs and Deserializer1D block inputs that are connected to AXI4-Stream int

Last post by mamorani « Fri Mar 12, 2021 9:18 am

by mamorani » Fri Mar 12, 2021 9:18 am

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304 Views

Last post by mamorani
Fri Mar 12, 2021 9:18 am
Rate mismatch at input of Deserializer1D block connected to port ' Change the rate to match the input rate for all oth

Last post by mamorani « Fri Mar 12, 2021 9:17 am

by mamorani » Fri Mar 12, 2021 9:17 am

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324 Views

Last post by mamorani
Fri Mar 12, 2021 9:17 am
Rate mismatch at output of Serializer1D block ', connected to port . Change the rate to match the output data rate for

Last post by mamorani « Fri Mar 12, 2021 9:16 am

by mamorani » Fri Mar 12, 2021 9:16 am

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262 Views

Last post by mamorani
Fri Mar 12, 2021 9:16 am
The valid signals must be modeled and assigned for AXI4-Stream interface on

Last post by mamorani « Fri Mar 12, 2021 9:16 am

by mamorani » Fri Mar 12, 2021 9:16 am

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269 Views

Last post by mamorani
Fri Mar 12, 2021 9:16 am
Rate mismatch at the output of Rate Transition block connected to port Change the output sample time of '' to match the

Last post by mamorani « Fri Mar 12, 2021 9:15 am

by mamorani » Fri Mar 12, 2021 9:15 am

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292 Views

Last post by mamorani
Fri Mar 12, 2021 9:15 am
All delay blocks inside sharable subsystems must have their \'initial condition\' set to zero.

Last post by mamorani « Thu Mar 11, 2021 4:09 pm

by mamorani » Thu Mar 11, 2021 4:09 pm

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265 Views

Last post by mamorani
Thu Mar 11, 2021 4:09 pm
Unsupported state element within sharing candidate

Last post by mamorani « Thu Mar 11, 2021 4:09 pm

by mamorani » Thu Mar 11, 2021 4:09 pm

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258 Views

Last post by mamorani
Thu Mar 11, 2021 4:09 pm
Subsystem is a shared partition, no need to share again

Last post by mamorani « Thu Mar 11, 2021 4:06 pm

by mamorani » Thu Mar 11, 2021 4:06 pm

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271 Views

Last post by mamorani
Thu Mar 11, 2021 4:06 pm
Atomic subsystem has multiple instances in different conditional subsystems

Last post by mamorani « Thu Mar 11, 2021 4:04 pm

by mamorani » Thu Mar 11, 2021 4:04 pm

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243 Views

Last post by mamorani
Thu Mar 11, 2021 4:04 pm
Delay balancing may fail, because this block is in a conditional subsystem and has pipeline delays

Last post by mamorani « Thu Mar 11, 2021 4:04 pm

by mamorani » Thu Mar 11, 2021 4:04 pm

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265 Views

Last post by mamorani
Thu Mar 11, 2021 4:04 pm
Resource sharing of blocks with latency which are data dependent is unsupported. For floating-point blocks, set the late

Last post by mamorani « Thu Mar 11, 2021 4:03 pm

by mamorani » Thu Mar 11, 2021 4:03 pm

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237 Views

Last post by mamorani
Thu Mar 11, 2021 4:03 pm
Sharing group contains blocks with pipeline delays.

Last post by mamorani « Thu Mar 11, 2021 4:03 pm

by mamorani » Thu Mar 11, 2021 4:03 pm

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274 Views

Last post by mamorani
Thu Mar 11, 2021 4:03 pm
Sharing group contains blocks with pipeline delays.

Last post by mamorani « Thu Mar 11, 2021 4:02 pm

by mamorani » Thu Mar 11, 2021 4:02 pm

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231 Views

Last post by mamorani
Thu Mar 11, 2021 4:02 pm
Single-rate sharing cannot be performed on sharing group sub-graphs containing feedback cycles.

Last post by mamorani « Thu Mar 11, 2021 4:01 pm

by mamorani » Thu Mar 11, 2021 4:01 pm

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234 Views

Last post by mamorani
Thu Mar 11, 2021 4:01 pm
For single-rate streaming, the streaming factor must be less than or equal to the Oversampling factor

Last post by mamorani « Thu Mar 11, 2021 4:00 pm

by mamorani » Thu Mar 11, 2021 4:00 pm

0 Replies

233 Views

Last post by mamorani
Thu Mar 11, 2021 4:00 pm
For single-rate sharing, the sharing factor must be less than or equal to the Oversampling factor.

Last post by mamorani « Thu Mar 11, 2021 4:00 pm

by mamorani » Thu Mar 11, 2021 4:00 pm

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220 Views

Last post by mamorani
Thu Mar 11, 2021 4:00 pm
Found at least two non-scalar signal data types of size and

Last post by mamorani « Thu Mar 11, 2021 3:59 pm

by mamorani » Thu Mar 11, 2021 3:59 pm

0 Replies

252 Views

Last post by mamorani
Thu Mar 11, 2021 3:59 pm
Vector size of is incompatible with streaming factor of

Last post by mamorani « Thu Mar 11, 2021 3:57 pm

by mamorani » Thu Mar 11, 2021 3:57 pm

0 Replies

225 Views

Last post by mamorani
Thu Mar 11, 2021 3:57 pm

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