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Unable to map floating-point Math Function block to Xilinx LogiCORE IP. Consider using Native Floating Point mode inst

Last post by mamorani « Fri Mar 12, 2021 3:17 pm

by mamorani » Fri Mar 12, 2021 3:17 pm

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252 Views

Last post by mamorani
Fri Mar 12, 2021 3:17 pm
Trigonometric Function is supported only in native floating-point mode

Last post by mamorani « Fri Mar 12, 2021 3:16 pm

by mamorani » Fri Mar 12, 2021 3:16 pm

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250 Views

Last post by mamorani
Fri Mar 12, 2021 3:16 pm
Sqrt is supported only in floating-point code generation mode.

Last post by mamorani « Fri Mar 12, 2021 3:16 pm

by mamorani » Fri Mar 12, 2021 3:16 pm

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215 Views

Last post by mamorani
Fri Mar 12, 2021 3:16 pm
Math Function is supported only in native floating-point mode.

Last post by mamorani « Fri Mar 12, 2021 3:15 pm

by mamorani » Fri Mar 12, 2021 3:15 pm

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335 Views

Last post by mamorani
Fri Mar 12, 2021 3:15 pm
Float Typecast is supported only in floating-point code generation mode.

Last post by mamorani « Fri Mar 12, 2021 3:15 pm

by mamorani » Fri Mar 12, 2021 3:15 pm

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263 Views

Last post by mamorani
Fri Mar 12, 2021 3:15 pm
Clock rate pipelining failed in which can be caused by signal logging. Disable logging of signals in the design

Last post by mamorani « Fri Mar 12, 2021 3:15 pm

by mamorani » Fri Mar 12, 2021 3:15 pm

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240 Views

Last post by mamorani
Fri Mar 12, 2021 3:15 pm
Cannot allocate sufficient delays for blocks in subsystem , which is in a loop. This subsystem and the loop may be crea

Last post by mamorani « Fri Mar 12, 2021 3:14 pm

by mamorani » Fri Mar 12, 2021 3:14 pm

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232 Views

Last post by mamorani
Fri Mar 12, 2021 3:14 pm
Target-specific code generation cannot complete for the following reason

Last post by mamorani « Fri Mar 12, 2021 3:14 pm

by mamorani » Fri Mar 12, 2021 3:14 pm

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228 Views

Last post by mamorani
Fri Mar 12, 2021 3:14 pm
Target device must be specified to generate Altera Megafunction IPs. Specify the device in the 'HDL Code Generation -> T

Last post by mamorani « Fri Mar 12, 2021 3:13 pm

by mamorani » Fri Mar 12, 2021 3:13 pm

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225 Views

Last post by mamorani
Fri Mar 12, 2021 3:13 pm
The cascade implementation of the Sum block requires a single vector as input

Last post by mamorani « Fri Mar 12, 2021 3:12 pm

by mamorani » Fri Mar 12, 2021 3:12 pm

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221 Views

Last post by mamorani
Fri Mar 12, 2021 3:12 pm
For streaming/sharing support, continuous sample time (= 0) is not allowed. Please use inherit (-1) or set an explicit s

Last post by mamorani « Fri Mar 12, 2021 3:11 pm

by mamorani » Fri Mar 12, 2021 3:11 pm

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250 Views

Last post by mamorani
Fri Mar 12, 2021 3:11 pm
State ports are not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 3:11 pm

by mamorani » Fri Mar 12, 2021 3:11 pm

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255 Views

Last post by mamorani
Fri Mar 12, 2021 3:11 pm
HDL support is not available for the single-rate processing mode. Set the ''Rate options'' setting to ''Allow multirate

Last post by mamorani « Fri Mar 12, 2021 3:10 pm

by mamorani » Fri Mar 12, 2021 3:10 pm

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221 Views

Last post by mamorani
Fri Mar 12, 2021 3:10 pm
Channel sharing is not supported for single input FIR

Last post by mamorani « Fri Mar 12, 2021 3:10 pm

by mamorani » Fri Mar 12, 2021 3:10 pm

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221 Views

Last post by mamorani
Fri Mar 12, 2021 3:10 pm
Block output is always a constant since the input contains no fractional bits; synthesis tools will eliminate this net

Last post by mamorani « Fri Mar 12, 2021 3:10 pm

by mamorani » Fri Mar 12, 2021 3:10 pm

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248 Views

Last post by mamorani
Fri Mar 12, 2021 3:10 pm
Block does not support 'double' and 'single' datatypes at input for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 3:09 pm

by mamorani » Fri Mar 12, 2021 3:09 pm

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209 Views

Last post by mamorani
Fri Mar 12, 2021 3:09 pm
Parameter in has been marked as tunable, but not defined as a Simulink.Parameter object. For HDL Code generation, eit

Last post by mamorani « Fri Mar 12, 2021 3:09 pm

by mamorani » Fri Mar 12, 2021 3:09 pm

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507 Views

Last post by mamorani
Fri Mar 12, 2021 3:09 pm
Data type of tunable structure parameter ' is ' In the base workspace, create a Simulink.Bus object and use its name a

Last post by mamorani « Fri Mar 12, 2021 3:08 pm

by mamorani » Fri Mar 12, 2021 3:08 pm

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221 Views

Last post by mamorani
Fri Mar 12, 2021 3:08 pm
Simscape blocks are not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 3:08 pm

by mamorani » Fri Mar 12, 2021 3:08 pm

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214 Views

Last post by mamorani
Fri Mar 12, 2021 3:08 pm
Auto routing of signals depend on the auto placement of blocks. Set the ''Auto blocks placement'' option under ''Layout

Last post by mamorani « Fri Mar 12, 2021 3:02 pm

by mamorani » Fri Mar 12, 2021 3:02 pm

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224 Views

Last post by mamorani
Fri Mar 12, 2021 3:02 pm
Validation model generation depends on the generated model. Set the ''Generated Model'' option under ''Model To Generate

Last post by mamorani « Fri Mar 12, 2021 3:02 pm

by mamorani » Fri Mar 12, 2021 3:02 pm

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208 Views

Last post by mamorani
Fri Mar 12, 2021 3:02 pm
Unable to map Sqrt block with 'rsqrt' function to Xilinx LogiCORE IP. Consider using Native Floating Point mode instead

Last post by mamorani « Fri Mar 12, 2021 3:01 pm

by mamorani » Fri Mar 12, 2021 3:01 pm

0 Replies

286 Views

Last post by mamorani
Fri Mar 12, 2021 3:01 pm
Round mode must be ''Nearest'' for floating-point support.

Last post by mamorani « Fri Mar 12, 2021 3:01 pm

by mamorani » Fri Mar 12, 2021 3:01 pm

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265 Views

Last post by mamorani
Fri Mar 12, 2021 3:01 pm
The Reset Port block is only supported for HDL Code generation when in a Synchronous subsystem. To correct this issue, a

Last post by mamorani « Fri Mar 12, 2021 3:01 pm

by mamorani » Fri Mar 12, 2021 3:01 pm

0 Replies

245 Views

Last post by mamorani
Fri Mar 12, 2021 3:01 pm
Model block has an empty ReferenceModelPrefix specified. This may cause HDL compilation issues due to name collisions b

Last post by mamorani « Fri Mar 12, 2021 3:00 pm

by mamorani » Fri Mar 12, 2021 3:00 pm

0 Replies

276 Views

Last post by mamorani
Fri Mar 12, 2021 3:00 pm

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