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Illegal conversion to/from floating point and fixed-point in Consider selecting ''Native Floating Point'' as the Float

Last post by mamorani « Fri Mar 12, 2021 5:05 pm

by mamorani » Fri Mar 12, 2021 5:05 pm

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293 Views

Last post by mamorani
Fri Mar 12, 2021 5:05 pm
Illegal block encountered in subsystem-level distributed pipelining or constrained output pipelining. You may put it ins

Last post by mamorani « Fri Mar 12, 2021 5:02 pm

by mamorani » Fri Mar 12, 2021 5:02 pm

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181 Views

Last post by mamorani
Fri Mar 12, 2021 5:02 pm
Model name or top-level subsystem should have an ASCII compliant name. HDL Coder does not support UTF-16 top level DUT

Last post by mamorani « Fri Mar 12, 2021 5:01 pm

by mamorani » Fri Mar 12, 2021 5:01 pm

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183 Views

Last post by mamorani
Fri Mar 12, 2021 5:01 pm
Using Constant High Z implementation can cause mismatch failures in the generated testbench

Last post by mamorani « Fri Mar 12, 2021 5:01 pm

by mamorani » Fri Mar 12, 2021 5:01 pm

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184 Views

Last post by mamorani
Fri Mar 12, 2021 5:01 pm
hdlgainblock was unable to get the Gain parameter value

Last post by mamorani « Fri Mar 12, 2021 5:00 pm

by mamorani » Fri Mar 12, 2021 5:00 pm

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195 Views

Last post by mamorani
Fri Mar 12, 2021 5:00 pm
Math function is not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 4:59 pm

by mamorani » Fri Mar 12, 2021 4:59 pm

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169 Views

Last post by mamorani
Fri Mar 12, 2021 4:59 pm
Fraction'' data type must be set to on the Lookup Table (n-D) for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 4:58 pm

by mamorani » Fri Mar 12, 2021 4:58 pm

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156 Views

Last post by mamorani
Fri Mar 12, 2021 4:58 pm
Fraction'' data type must be set to on the Lookup Table (n-D) for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 4:56 pm

by mamorani » Fri Mar 12, 2021 4:56 pm

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189 Views

Last post by mamorani
Fri Mar 12, 2021 4:56 pm
Floating-point data type not supported on port of the block

Last post by mamorani « Fri Mar 12, 2021 4:56 pm

by mamorani » Fri Mar 12, 2021 4:56 pm

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225 Views

Last post by mamorani
Fri Mar 12, 2021 4:56 pm
When using fixed-point data, the specified custom latency for block is not supported. The custom latency should be le

Last post by mamorani « Fri Mar 12, 2021 4:55 pm

by mamorani » Fri Mar 12, 2021 4:55 pm

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181 Views

Last post by mamorani
Fri Mar 12, 2021 4:55 pm
is not supported as an extrapolation method by the Lookup Table (n-D) for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 4:54 pm

by mamorani » Fri Mar 12, 2021 4:54 pm

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172 Views

Last post by mamorani
Fri Mar 12, 2021 4:54 pm
The enable port of an enabled subsystem must have a boolean or ufix1 type

Last post by mamorani « Fri Mar 12, 2021 4:53 pm

by mamorani » Fri Mar 12, 2021 4:53 pm

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193 Views

Last post by mamorani
Fri Mar 12, 2021 4:53 pm
Block is not supported in this configuration for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 4:52 pm

by mamorani » Fri Mar 12, 2021 4:52 pm

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176 Views

Last post by mamorani
Fri Mar 12, 2021 4:52 pm
There are more than one DSP Builder ports named in the generated HDL. Please examine the Altera subsystem in your mode

Last post by mamorani « Fri Mar 12, 2021 4:52 pm

by mamorani » Fri Mar 12, 2021 4:52 pm

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19140 Views

Last post by mamorani
Fri Mar 12, 2021 4:52 pm
must be default value on the System Generator Subsystem or DSPBA Subsystem

Last post by mamorani « Fri Mar 12, 2021 4:50 pm

by mamorani » Fri Mar 12, 2021 4:50 pm

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194 Views

Last post by mamorani
Fri Mar 12, 2021 4:50 pm
Altera DSP Builder Advanced Blockset does not support Verilog code generation.

Last post by mamorani « Fri Mar 12, 2021 4:49 pm

by mamorani » Fri Mar 12, 2021 4:49 pm

0 Replies

434 Views

Last post by mamorani
Fri Mar 12, 2021 4:49 pm
Floating point types are not supported on the interface of DSPBA subsystem

Last post by mamorani « Fri Mar 12, 2021 4:46 pm

by mamorani » Fri Mar 12, 2021 4:46 pm

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173 Views

Last post by mamorani
Fri Mar 12, 2021 4:46 pm
DSPBA subsystem is not inside of code generation subsystem

Last post by mamorani « Fri Mar 12, 2021 4:46 pm

by mamorani » Fri Mar 12, 2021 4:46 pm

0 Replies

181 Views

Last post by mamorani
Fri Mar 12, 2021 4:46 pm
Different frequencies are set in HDL Workflow Advisor and in DSPBA signals block

Last post by mamorani « Fri Mar 12, 2021 4:45 pm

by mamorani » Fri Mar 12, 2021 4:45 pm

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196 Views

Last post by mamorani
Fri Mar 12, 2021 4:45 pm
The top level subsystem cannot be a DSPBA Subsystem

Last post by mamorani « Fri Mar 12, 2021 4:45 pm

by mamorani » Fri Mar 12, 2021 4:45 pm

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181 Views

Last post by mamorani
Fri Mar 12, 2021 4:45 pm
Device set in ' is not ', which has been set through HDL Workflow Advisor

Last post by mamorani « Fri Mar 12, 2021 4:44 pm

by mamorani » Fri Mar 12, 2021 4:44 pm

0 Replies

173 Views

Last post by mamorani
Fri Mar 12, 2021 4:44 pm
Gain block with fixed-point input and floating-point gain parameter is not supported. Please specify proper 'Parameter d

Last post by mamorani « Fri Mar 12, 2021 3:53 pm

by mamorani » Fri Mar 12, 2021 3:53 pm

0 Replies

222 Views

Last post by mamorani
Fri Mar 12, 2021 3:53 pm
Math Function block (as Hermitian) cannot have ''double'' or ''single'' input data type

Last post by mamorani « Fri Mar 12, 2021 3:53 pm

by mamorani » Fri Mar 12, 2021 3:53 pm

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197 Views

Last post by mamorani
Fri Mar 12, 2021 3:53 pm
The ''AddClockEnablePort'' parameter will be removed in the future. To control RAM inference during synthesis, use the '

Last post by mamorani « Fri Mar 12, 2021 3:45 pm

by mamorani » Fri Mar 12, 2021 3:45 pm

0 Replies

166 Views

Last post by mamorani
Fri Mar 12, 2021 3:45 pm
HDL code generation is not supported for this counter block when it is in a resettable subsystem. Consider using the HDL

Last post by mamorani « Fri Mar 12, 2021 3:45 pm

by mamorani » Fri Mar 12, 2021 3:45 pm

0 Replies

176 Views

Last post by mamorani
Fri Mar 12, 2021 3:45 pm

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