Signal Processing

New Topic

3049 topics

Page 62 of 122
- Jump to page:
Previous
1
…
60
61
62
63
64
…
122
Next

Topics

Replies

Views

Last post

Illegal conversion to/from floating point and fixed-point in Consider selecting ''Native Floating Point'' as the Float

Last post by mamorani « Fri Mar 12, 2021 5:05 pm

by mamorani » Fri Mar 12, 2021 5:05 pm

0 Replies

397 Views

Last post by mamorani
Fri Mar 12, 2021 5:05 pm
Illegal block encountered in subsystem-level distributed pipelining or constrained output pipelining. You may put it ins

Last post by mamorani « Fri Mar 12, 2021 5:02 pm

by mamorani » Fri Mar 12, 2021 5:02 pm

0 Replies

266 Views

Last post by mamorani
Fri Mar 12, 2021 5:02 pm
Model name or top-level subsystem should have an ASCII compliant name. HDL Coder does not support UTF-16 top level DUT

Last post by mamorani « Fri Mar 12, 2021 5:01 pm

by mamorani » Fri Mar 12, 2021 5:01 pm

0 Replies

280 Views

Last post by mamorani
Fri Mar 12, 2021 5:01 pm
Using Constant High Z implementation can cause mismatch failures in the generated testbench

Last post by mamorani « Fri Mar 12, 2021 5:01 pm

by mamorani » Fri Mar 12, 2021 5:01 pm

0 Replies

289 Views

Last post by mamorani
Fri Mar 12, 2021 5:01 pm
hdlgainblock was unable to get the Gain parameter value

Last post by mamorani « Fri Mar 12, 2021 5:00 pm

by mamorani » Fri Mar 12, 2021 5:00 pm

0 Replies

289 Views

Last post by mamorani
Fri Mar 12, 2021 5:00 pm
Math function is not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 4:59 pm

by mamorani » Fri Mar 12, 2021 4:59 pm

0 Replies

260 Views

Last post by mamorani
Fri Mar 12, 2021 4:59 pm
Fraction'' data type must be set to on the Lookup Table (n-D) for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 4:58 pm

by mamorani » Fri Mar 12, 2021 4:58 pm

0 Replies

248 Views

Last post by mamorani
Fri Mar 12, 2021 4:58 pm
Fraction'' data type must be set to on the Lookup Table (n-D) for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 4:56 pm

by mamorani » Fri Mar 12, 2021 4:56 pm

0 Replies

285 Views

Last post by mamorani
Fri Mar 12, 2021 4:56 pm
Floating-point data type not supported on port of the block

Last post by mamorani « Fri Mar 12, 2021 4:56 pm

by mamorani » Fri Mar 12, 2021 4:56 pm

0 Replies

315 Views

Last post by mamorani
Fri Mar 12, 2021 4:56 pm
When using fixed-point data, the specified custom latency for block is not supported. The custom latency should be le

Last post by mamorani « Fri Mar 12, 2021 4:55 pm

by mamorani » Fri Mar 12, 2021 4:55 pm

0 Replies

279 Views

Last post by mamorani
Fri Mar 12, 2021 4:55 pm
is not supported as an extrapolation method by the Lookup Table (n-D) for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 4:54 pm

by mamorani » Fri Mar 12, 2021 4:54 pm

0 Replies

270 Views

Last post by mamorani
Fri Mar 12, 2021 4:54 pm
The enable port of an enabled subsystem must have a boolean or ufix1 type

Last post by mamorani « Fri Mar 12, 2021 4:53 pm

by mamorani » Fri Mar 12, 2021 4:53 pm

0 Replies

290 Views

Last post by mamorani
Fri Mar 12, 2021 4:53 pm
Block is not supported in this configuration for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 4:52 pm

by mamorani » Fri Mar 12, 2021 4:52 pm

0 Replies

272 Views

Last post by mamorani
Fri Mar 12, 2021 4:52 pm
There are more than one DSP Builder ports named in the generated HDL. Please examine the Altera subsystem in your mode

Last post by mamorani « Fri Mar 12, 2021 4:52 pm

by mamorani » Fri Mar 12, 2021 4:52 pm

0 Replies

19232 Views

Last post by mamorani
Fri Mar 12, 2021 4:52 pm
must be default value on the System Generator Subsystem or DSPBA Subsystem

Last post by mamorani « Fri Mar 12, 2021 4:50 pm

by mamorani » Fri Mar 12, 2021 4:50 pm

0 Replies

299 Views

Last post by mamorani
Fri Mar 12, 2021 4:50 pm
Altera DSP Builder Advanced Blockset does not support Verilog code generation.

Last post by mamorani « Fri Mar 12, 2021 4:49 pm

by mamorani » Fri Mar 12, 2021 4:49 pm

0 Replies

536 Views

Last post by mamorani
Fri Mar 12, 2021 4:49 pm
Floating point types are not supported on the interface of DSPBA subsystem

Last post by mamorani « Fri Mar 12, 2021 4:46 pm

by mamorani » Fri Mar 12, 2021 4:46 pm

0 Replies

269 Views

Last post by mamorani
Fri Mar 12, 2021 4:46 pm
DSPBA subsystem is not inside of code generation subsystem

Last post by mamorani « Fri Mar 12, 2021 4:46 pm

by mamorani » Fri Mar 12, 2021 4:46 pm

0 Replies

271 Views

Last post by mamorani
Fri Mar 12, 2021 4:46 pm
Different frequencies are set in HDL Workflow Advisor and in DSPBA signals block

Last post by mamorani « Fri Mar 12, 2021 4:45 pm

by mamorani » Fri Mar 12, 2021 4:45 pm

0 Replies

280 Views

Last post by mamorani
Fri Mar 12, 2021 4:45 pm
The top level subsystem cannot be a DSPBA Subsystem

Last post by mamorani « Fri Mar 12, 2021 4:45 pm

by mamorani » Fri Mar 12, 2021 4:45 pm

0 Replies

264 Views

Last post by mamorani
Fri Mar 12, 2021 4:45 pm
Device set in ' is not ', which has been set through HDL Workflow Advisor

Last post by mamorani « Fri Mar 12, 2021 4:44 pm

by mamorani » Fri Mar 12, 2021 4:44 pm

0 Replies

262 Views

Last post by mamorani
Fri Mar 12, 2021 4:44 pm
Gain block with fixed-point input and floating-point gain parameter is not supported. Please specify proper 'Parameter d

Last post by mamorani « Fri Mar 12, 2021 3:53 pm

by mamorani » Fri Mar 12, 2021 3:53 pm

0 Replies

318 Views

Last post by mamorani
Fri Mar 12, 2021 3:53 pm
Math Function block (as Hermitian) cannot have ''double'' or ''single'' input data type

Last post by mamorani « Fri Mar 12, 2021 3:53 pm

by mamorani » Fri Mar 12, 2021 3:53 pm

0 Replies

293 Views

Last post by mamorani
Fri Mar 12, 2021 3:53 pm
The ''AddClockEnablePort'' parameter will be removed in the future. To control RAM inference during synthesis, use the '

Last post by mamorani « Fri Mar 12, 2021 3:45 pm

by mamorani » Fri Mar 12, 2021 3:45 pm

0 Replies

259 Views

Last post by mamorani
Fri Mar 12, 2021 3:45 pm
HDL code generation is not supported for this counter block when it is in a resettable subsystem. Consider using the HDL

Last post by mamorani « Fri Mar 12, 2021 3:45 pm

by mamorani » Fri Mar 12, 2021 3:45 pm

0 Replies

275 Views

Last post by mamorani
Fri Mar 12, 2021 3:45 pm

New Topic

3049 topics

Page 62 of 122
- Jump to page:
Previous
1
…
60
61
62
63
64
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 2 guests

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum