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Unable to map signal to the model port as the " signal from the same interface is already mapped to the model port

Last post by mamorani « Sat Mar 13, 2021 10:40 am

by mamorani » Sat Mar 13, 2021 10:40 am

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Last post by mamorani
Sat Mar 13, 2021 10:40 am
Unable to assign interface protocol signal to model port as it is already assigned to model port

Last post by mamorani « Sat Mar 13, 2021 10:39 am

by mamorani » Sat Mar 13, 2021 10:39 am

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375 Views

Last post by mamorani
Sat Mar 13, 2021 10:39 am
No driver block was generated for port(s) mapped to interface in the software interface model

Last post by mamorani « Sat Mar 13, 2021 10:38 am

by mamorani » Sat Mar 13, 2021 10:38 am

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279 Views

Last post by mamorani
Sat Mar 13, 2021 10:38 am
"MasterChannelNumber" or "SlaveChannelNumber" can only be 0 or 1. It is recommended that you use "MasterChannelEnable" a

Last post by mamorani « Sat Mar 13, 2021 10:38 am

by mamorani » Sat Mar 13, 2021 10:38 am

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255 Views

Last post by mamorani
Sat Mar 13, 2021 10:38 am
The fractional length of the fixed point type does not match. is ,number,integer is

Last post by mamorani « Sat Mar 13, 2021 10:37 am

by mamorani » Sat Mar 13, 2021 10:37 am

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271 Views

Last post by mamorani
Sat Mar 13, 2021 10:37 am
Function isTypeEqual is not supported when the word length of both fixed point types are flexible.

Last post by mamorani « Sat Mar 13, 2021 10:36 am

by mamorani » Sat Mar 13, 2021 10:36 am

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251 Views

Last post by mamorani
Sat Mar 13, 2021 10:36 am
The word length of the fixed point type does not match. is ,number,integer is flexible up to

Last post by mamorani « Sat Mar 13, 2021 10:36 am

by mamorani » Sat Mar 13, 2021 10:36 am

0 Replies

601 Views

Last post by mamorani
Sat Mar 13, 2021 10:36 am
The sign bit of the fixed point type does not match. is ,number,integer is number,integer}

Last post by mamorani « Sat Mar 13, 2021 10:35 am

by mamorani » Sat Mar 13, 2021 10:35 am

0 Replies

271 Views

Last post by mamorani
Sat Mar 13, 2021 10:35 am
Failed to create channel ' because this channel already exists.

Last post by mamorani « Sat Mar 13, 2021 10:35 am

by mamorani » Sat Mar 13, 2021 10:35 am

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253 Views

Last post by mamorani
Sat Mar 13, 2021 10:35 am
The custom interface class ' included in the reference design ' ' does not exist on the MATLAB path. Please contact the

Last post by mamorani « Sat Mar 13, 2021 10:34 am

by mamorani » Sat Mar 13, 2021 10:34 am

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258 Views

Last post by mamorani
Sat Mar 13, 2021 10:34 am
Clock frequency must be between MHz and MHz, inclusive. The value MHz is outside this range

Last post by mamorani « Sat Mar 13, 2021 10:34 am

by mamorani » Sat Mar 13, 2021 10:34 am

0 Replies

292 Views

Last post by mamorani
Sat Mar 13, 2021 10:34 am
Cannot specify both "MasterChannelEnable"/"SlaveChannelEnable" and "MasterChannelNumber"/"SlaveChannelNumber". Please on

Last post by mamorani « Sat Mar 13, 2021 10:33 am

by mamorani » Sat Mar 13, 2021 10:33 am

0 Replies

242 Views

Last post by mamorani
Sat Mar 13, 2021 10:33 am
All the DUT ports connecting to the interface must be running at the fastest rate in the generated DUT HDL code. Port

Last post by mamorani « Sat Mar 13, 2021 10:32 am

by mamorani » Sat Mar 13, 2021 10:32 am

0 Replies

281 Views

Last post by mamorani
Sat Mar 13, 2021 10:32 am
Bus members do not match on name, or do not match in order. bus type contains members bus type contains members

Last post by mamorani « Sat Mar 13, 2021 10:29 am

by mamorani » Sat Mar 13, 2021 10:29 am

0 Replies

271 Views

Last post by mamorani
Sat Mar 13, 2021 10:29 am
Multiple AXI4-Stream interfaces cannot be mapped to vector ports. To use multiple AXI4-Stream interfaces, you must map o

Last post by mamorani « Sat Mar 13, 2021 10:29 am

by mamorani » Sat Mar 13, 2021 10:29 am

0 Replies

288 Views

Last post by mamorani
Sat Mar 13, 2021 10:29 am
Interface " cannot be mapped to port . When one AXI4-Stream interface is mapped to a vector port, additional AXI4-Strea

Last post by mamorani « Sat Mar 13, 2021 10:28 am

by mamorani » Sat Mar 13, 2021 10:28 am

0 Replies

304 Views

Last post by mamorani
Sat Mar 13, 2021 10:28 am
In Generic IP, only "MasterChannelEnable" and "SlaveChannelEnable" parameters are supported.

Last post by mamorani « Sat Mar 13, 2021 10:28 am

by mamorani » Sat Mar 13, 2021 10:28 am

0 Replies

262 Views

Last post by mamorani
Sat Mar 13, 2021 10:28 am
TargetAddressSegments must be a cell array of cell arrays of the format:\n '{'''[bd address segment]'', [offset], [range

Last post by mamorani « Sat Mar 13, 2021 10:27 am

by mamorani » Sat Mar 13, 2021 10:27 am

0 Replies

281 Views

Last post by mamorani
Sat Mar 13, 2021 10:27 am
The AXI4 Master interface requires that at least one of "ReadSupport" or "WriteSupport" be enabled

Last post by mamorani « Sat Mar 13, 2021 9:54 am

by mamorani » Sat Mar 13, 2021 9:54 am

0 Replies

288 Views

Last post by mamorani
Sat Mar 13, 2021 9:54 am
In Generic IP, the parameter is not supported.

Last post by mamorani « Sat Mar 13, 2021 9:50 am

by mamorani » Sat Mar 13, 2021 9:50 am

0 Replies

277 Views

Last post by mamorani
Sat Mar 13, 2021 9:50 am
The AXI Master data widths for the read and write channels must match.

Last post by mamorani « Sat Mar 13, 2021 9:50 am

by mamorani » Sat Mar 13, 2021 9:50 am

0 Replies

289 Views

Last post by mamorani
Sat Mar 13, 2021 9:50 am
Sub-program should be described by appropriate comments

Last post by mamorani « Sat Mar 13, 2021 9:47 am

by mamorani » Sat Mar 13, 2021 9:47 am

0 Replies

274 Views

Last post by mamorani
Sat Mar 13, 2021 9:47 am
Each file's reference should be specified by a relative path (return to the master directory once)

Last post by mamorani « Sat Mar 13, 2021 9:46 am

by mamorani » Sat Mar 13, 2021 9:46 am

0 Replies

267 Views

Last post by mamorani
Sat Mar 13, 2021 9:46 am
File references must be relative path names including the master directory

Last post by mamorani « Sat Mar 13, 2021 9:46 am

by mamorani » Sat Mar 13, 2021 9:46 am

0 Replies

271 Views

Last post by mamorani
Sat Mar 13, 2021 9:46 am
Non-integer type used in the declaration of a generic may be unsynthesizable

Last post by mamorani « Sat Mar 13, 2021 9:45 am

by mamorani » Sat Mar 13, 2021 9:45 am

0 Replies

258 Views

Last post by mamorani
Sat Mar 13, 2021 9:45 am

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