Signal Processing

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Following top level subsystem and/or port names have mixed cases and/or lengths greater than 16 characters

Last post by mamorani « Sun Mar 14, 2021 8:25 pm

by mamorani » Sun Mar 14, 2021 8:25 pm

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Last post by mamorani
Sun Mar 14, 2021 8:25 pm
Following subsystems have names that are less than 2 characters or greater than 32 characters.

Last post by mamorani « Sun Mar 14, 2021 8:25 pm

by mamorani » Sun Mar 14, 2021 8:25 pm

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Last post by mamorani
Sun Mar 14, 2021 8:25 pm
VHDL entity and architecture are written to separate files.

Last post by mamorani « Sun Mar 14, 2021 8:25 pm

by mamorani » Sun Mar 14, 2021 8:25 pm

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Last post by mamorani
Sun Mar 14, 2021 8:25 pm
Recommended naming conventions are not followed by the reset signal

Last post by mamorani « Sun Mar 14, 2021 8:24 pm

by mamorani » Sun Mar 14, 2021 8:24 pm

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Last post by mamorani
Sun Mar 14, 2021 8:24 pm
Following ports and/or signals from the blocks have names that are less than 2 characters or greater than 40 characters.

Last post by mamorani « Sun Mar 14, 2021 8:24 pm

by mamorani » Sun Mar 14, 2021 8:24 pm

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Last post by mamorani
Sun Mar 14, 2021 8:24 pm
The postfix for the package file is ' . Industry standards recommend '_pac' as the postfix name

Last post by mamorani « Sun Mar 14, 2021 8:24 pm

by mamorani » Sun Mar 14, 2021 8:24 pm

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Last post by mamorani
Sun Mar 14, 2021 8:24 pm
Following blocks and/or signals from the blocks contain standard keywords used by different EDA tools

Last post by mamorani « Sun Mar 14, 2021 8:23 pm

by mamorani » Sun Mar 14, 2021 8:23 pm

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Last post by mamorani
Sun Mar 14, 2021 8:23 pm
'MaskParameterAsGeneric'' is turned on. This can result in the use of generics at top level

Last post by mamorani « Sun Mar 14, 2021 8:15 pm

by mamorani » Sun Mar 14, 2021 8:15 pm

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Last post by mamorani
Sun Mar 14, 2021 8:15 pm
The VHDL file extension is . File names should have an extension of ''.vhd'' or ''.vhdl'

Last post by mamorani « Sun Mar 14, 2021 8:15 pm

by mamorani » Sun Mar 14, 2021 8:15 pm

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Last post by mamorani
Sun Mar 14, 2021 8:15 pm
ClockInputs property is set to ''Multiple''. This can introduce more than one clock in the design and hierarchies with d

Last post by mamorani « Sun Mar 14, 2021 8:15 pm

by mamorani » Sun Mar 14, 2021 8:15 pm

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772 Views

Last post by mamorani
Sun Mar 14, 2021 8:15 pm
Recommended naming conventions are not followed by the clock signal

Last post by mamorani « Sun Mar 14, 2021 8:14 pm

by mamorani » Sun Mar 14, 2021 8:14 pm

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Last post by mamorani
Sun Mar 14, 2021 8:14 pm
The VHDL architecture name for generated HDL code is Architecture name should contain ''rtl'

Last post by mamorani « Sun Mar 14, 2021 8:14 pm

by mamorani » Sun Mar 14, 2021 8:14 pm

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Last post by mamorani
Sun Mar 14, 2021 8:14 pm
Data type display on signals and ports is disabled.

Last post by mamorani « Sun Mar 14, 2021 8:14 pm

by mamorani » Sun Mar 14, 2021 8:14 pm

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729 Views

Last post by mamorani
Sun Mar 14, 2021 8:14 pm
The system for HDL code generation contains algebraic loop. HDL Coder does not support code generation for system contai

Last post by mamorani « Sun Mar 14, 2021 8:13 pm

by mamorani » Sun Mar 14, 2021 8:13 pm

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803 Views

Last post by mamorani
Sun Mar 14, 2021 8:13 pm
hdlmodelchecker requires a model or a full path to the subsystem to be specified. Use hdlmodelchecker('modelname') or hd

Last post by mamorani « Sun Mar 14, 2021 8:13 pm

by mamorani » Sun Mar 14, 2021 8:13 pm

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713 Views

Last post by mamorani
Sun Mar 14, 2021 8:13 pm
Altera devices generally perform better on Asynchronous reset; you can update 'ResetType' to 'Asynchronous' for the foll

Last post by mamorani « Sun Mar 14, 2021 8:13 pm

by mamorani » Sun Mar 14, 2021 8:13 pm

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718 Views

Last post by mamorani
Sun Mar 14, 2021 8:13 pm
Xilinx devices generally perform better on synchronous reset; you can update 'ResetType' to 'Synchronous' for the follow

Last post by mamorani « Sun Mar 14, 2021 8:12 pm

by mamorani » Sun Mar 14, 2021 8:12 pm

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730 Views

Last post by mamorani
Sun Mar 14, 2021 8:12 pm
The following blocks should have parameter ''MATLAB Function fimath'' set to ''Other:User Defined''.The fimath string sh

Last post by mamorani « Sun Mar 14, 2021 8:11 pm

by mamorani » Sun Mar 14, 2021 8:11 pm

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Last post by mamorani
Sun Mar 14, 2021 8:11 pm
The following blocks have ports with greater than 2 dimensions. HDL Coder will not be able to generate code for this mat

Last post by mamorani « Sun Mar 14, 2021 8:11 pm

by mamorani » Sun Mar 14, 2021 8:11 pm

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771 Views

Last post by mamorani
Sun Mar 14, 2021 8:11 pm
Workflow checks for downstream integration, co-simulation, synthesis etc.

Last post by mamorani « Sun Mar 14, 2021 8:10 pm

by mamorani » Sun Mar 14, 2021 8:10 pm

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698 Views

Last post by mamorani
Sun Mar 14, 2021 8:10 pm
Check model for DO-254 specific rule compliance

Last post by mamorani « Sun Mar 14, 2021 8:10 pm

by mamorani » Sun Mar 14, 2021 8:10 pm

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783 Views

Last post by mamorani
Sun Mar 14, 2021 8:10 pm
HDL code generation ignores signals with signal object storage class specified as ''ExportedGlobal'' , ''ImportedExtern'

Last post by mamorani « Sun Mar 14, 2021 8:09 pm

by mamorani » Sun Mar 14, 2021 8:09 pm

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775 Views

Last post by mamorani
Sun Mar 14, 2021 8:09 pm
Check whether signal object storage class is ''ExportedGlobal'' or ''ImportedExtern'' or ''ImportedExternPointer''

Last post by mamorani « Sun Mar 14, 2021 8:09 pm

by mamorani » Sun Mar 14, 2021 8:09 pm

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Last post by mamorani
Sun Mar 14, 2021 8:09 pm
Check for unsupported storage class for signal objects

Last post by mamorani « Sun Mar 14, 2021 8:09 pm

by mamorani » Sun Mar 14, 2021 8:09 pm

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805 Views

Last post by mamorani
Sun Mar 14, 2021 8:09 pm
block introduces latency but might report an incorrect value for vector inputs. Use the generated model to see the laten

Last post by mamorani « Sun Mar 14, 2021 8:09 pm

by mamorani » Sun Mar 14, 2021 8:09 pm

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749 Views

Last post by mamorani
Sun Mar 14, 2021 8:09 pm

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