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Sine Wave block must have Sample mode set to Discrete.

Last post by omidrostaei « Tue Mar 02, 2021 5:27 pm

by omidrostaei » Tue Mar 02, 2021 5:27 pm

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Last post by omidrostaei
Tue Mar 02, 2021 5:27 pm
Sine Wave block must have Computation method set to Table.

Last post by omidrostaei « Tue Mar 02, 2021 5:27 pm

by omidrostaei » Tue Mar 02, 2021 5:27 pm

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Last post by omidrostaei
Tue Mar 02, 2021 5:27 pm
HDL code generation support for the NCO block will be removed in a future version. Use the NCO HDL Optimized block inste

Last post by omidrostaei « Tue Mar 02, 2021 5:26 pm

by omidrostaei » Tue Mar 02, 2021 5:26 pm

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476 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:26 pm
NCO with a quarter-wave lookup table of 2 or fewer elements is not allowed. The quantized accumulator size should be gre

Last post by omidrostaei « Tue Mar 02, 2021 5:25 pm

by omidrostaei » Tue Mar 02, 2021 5:25 pm

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414 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:25 pm
NCO block with vector inputs and dithering is not supported.

Last post by omidrostaei « Tue Mar 02, 2021 5:25 pm

by omidrostaei » Tue Mar 02, 2021 5:25 pm

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413 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:25 pm
HDL support is not available for double output.

Last post by omidrostaei « Tue Mar 02, 2021 5:23 pm

by omidrostaei » Tue Mar 02, 2021 5:23 pm

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348 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:23 pm
Input and output(s) of the Multiport Selector block must all be complex or all be real.

Last post by omidrostaei « Tue Mar 02, 2021 5:23 pm

by omidrostaei » Tue Mar 02, 2021 5:23 pm

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394 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:23 pm
The validation model may produce assertions due to differences in the internal dither added. The differences can be avoi

Last post by omidrostaei « Tue Mar 02, 2021 5:22 pm

by omidrostaei » Tue Mar 02, 2021 5:22 pm

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465 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:22 pm
HDL code generation is not supported for dsp.Delay with Reset input.

Last post by omidrostaei « Tue Mar 02, 2021 5:22 pm

by omidrostaei » Tue Mar 02, 2021 5:22 pm

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424 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:22 pm
HDL code generation is not supported for frame delays.

Last post by omidrostaei « Tue Mar 02, 2021 5:22 pm

by omidrostaei » Tue Mar 02, 2021 5:22 pm

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434 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:22 pm
Integer delays can be mapped to RAMs only when initial condition is set to 0.

Last post by omidrostaei « Tue Mar 02, 2021 5:21 pm

by omidrostaei » Tue Mar 02, 2021 5:21 pm

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365 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:21 pm
HDL code generation is not supported for the Control port (reset).

Last post by omidrostaei « Tue Mar 02, 2021 5:21 pm

by omidrostaei » Tue Mar 02, 2021 5:21 pm

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428 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:21 pm
HDL support is not available for the single rate mode. Set the Sample-based mode setting to ''Allow multirate''.

Last post by omidrostaei « Tue Mar 02, 2021 5:20 pm

by omidrostaei » Tue Mar 02, 2021 5:20 pm

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359 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:20 pm
The input rate of Downsample block cannot be zero or Inf.

Last post by omidrostaei « Tue Mar 02, 2021 5:20 pm

by omidrostaei » Tue Mar 02, 2021 5:20 pm

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342 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:20 pm
System objects do not support structures. Type designoption,or validstructures to get a list of the supported System ob

Last post by omidrostaei « Tue Mar 02, 2021 5:20 pm

by omidrostaei » Tue Mar 02, 2021 5:20 pm

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336 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:20 pm
The vectors ''Frequencies'' and ''GroupDelay'' must have the same length.

Last post by omidrostaei « Tue Mar 02, 2021 5:18 pm

by omidrostaei » Tue Mar 02, 2021 5:18 pm

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353 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:18 pm
The first element of the ''Frequencies'' vector must be 0 and the last element Fs/2.

Last post by omidrostaei « Tue Mar 02, 2021 5:18 pm

by omidrostaei » Tue Mar 02, 2021 5:18 pm

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480 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:18 pm
The ''Frequencies'' vector must be monotonically increasing..

Last post by omidrostaei « Tue Mar 02, 2021 5:17 pm

by omidrostaei » Tue Mar 02, 2021 5:17 pm

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351 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:17 pm
The first element of the ''Frequencies'' vector must be 0 and the last element 1.

Last post by omidrostaei « Tue Mar 02, 2021 5:17 pm

by omidrostaei » Tue Mar 02, 2021 5:17 pm

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385 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:17 pm
Specifications must be provided in dB for this response.

Last post by omidrostaei « Tue Mar 02, 2021 5:16 pm

by omidrostaei » Tue Mar 02, 2021 5:16 pm

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347 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:16 pm
F0 cannot be 0 or 1 for specification type ''N,F0,Qa,Gref,G0'', if you want to design a shelving filter you may use spec

Last post by omidrostaei « Tue Mar 02, 2021 5:16 pm

by omidrostaei » Tue Mar 02, 2021 5:16 pm

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361 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:16 pm
Valid values for the property are The value has been rounded to .

Last post by omidrostaei « Tue Mar 02, 2021 5:15 pm

by omidrostaei » Tue Mar 02, 2021 5:15 pm

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331 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:15 pm
When the property is true, a sampling frequency of 48kHz is assumed. Use the method to control the value of the samplin

Last post by omidrostaei « Tue Mar 02, 2021 5:14 pm

by omidrostaei » Tue Mar 02, 2021 5:14 pm

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331 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:14 pm
Adjacent frequency bands must have the same frequency response at their junction

Last post by omidrostaei « Tue Mar 02, 2021 5:13 pm

by omidrostaei » Tue Mar 02, 2021 5:13 pm

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361 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:13 pm
The (i-1)-th and i-th frequency bands must be separated by a don''t care region.

Last post by omidrostaei « Tue Mar 02, 2021 5:13 pm

by omidrostaei » Tue Mar 02, 2021 5:13 pm

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356 Views

Last post by omidrostaei
Tue Mar 02, 2021 5:13 pm

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