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Only hard decision decoding is supported for HDL code generation.

Last post by omidrostaei « Sun Mar 14, 2021 5:17 pm

by omidrostaei » Sun Mar 14, 2021 5:17 pm

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Last post by omidrostaei
Sun Mar 14, 2021 5:17 pm
HDL Code generation of the M-PSK Modulator is only supported for M = 2,4, or 8.

Last post by omidrostaei « Sun Mar 14, 2021 5:17 pm

by omidrostaei » Sun Mar 14, 2021 5:17 pm

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332 Views

Last post by omidrostaei
Sun Mar 14, 2021 5:17 pm
HDL code generation for PSK Modulation is not supported for Double and Single data types. Convert the data types to fixe

Last post by omidrostaei « Sun Mar 14, 2021 5:16 pm

by omidrostaei » Sun Mar 14, 2021 5:16 pm

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378 Views

Last post by omidrostaei
Sun Mar 14, 2021 5:16 pm
HDL code generation is only supported for Hard Decision Decoding.

Last post by omidrostaei « Sun Mar 14, 2021 5:16 pm

by omidrostaei » Sun Mar 14, 2021 5:16 pm

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319 Views

Last post by omidrostaei
Sun Mar 14, 2021 5:16 pm
HDL Code generation of the M-PSK Demodulator is only supported for M = 2,4, or 8.

Last post by omidrostaei « Sun Mar 14, 2021 5:16 pm

by omidrostaei » Sun Mar 14, 2021 5:16 pm

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321 Views

Last post by omidrostaei
Sun Mar 14, 2021 5:16 pm
HDL code generation for PSK demodulation is not supported for Double and Single data types. Convert the data types to fi

Last post by omidrostaei « Sun Mar 14, 2021 5:15 pm

by omidrostaei » Sun Mar 14, 2021 5:15 pm

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434 Views

Last post by omidrostaei
Sun Mar 14, 2021 5:15 pm
PN Generator is not supported for HDL code generation inside a Triggered Subsystem when the "Use trigger signal as clock

Last post by omidrostaei « Sun Mar 14, 2021 4:36 pm

by omidrostaei » Sun Mar 14, 2021 4:36 pm

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375 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:36 pm
PN Generator does not support an output of type double.

Last post by omidrostaei « Sun Mar 14, 2021 4:36 pm

by omidrostaei » Sun Mar 14, 2021 4:36 pm

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300 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:36 pm
PN Generator Samples per frame parameter must be 1.

Last post by omidrostaei « Sun Mar 14, 2021 4:36 pm

by omidrostaei » Sun Mar 14, 2021 4:36 pm

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319 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:36 pm
The PN Generator mask input port must have type ufix1.

Last post by omidrostaei « Sun Mar 14, 2021 4:36 pm

by omidrostaei » Sun Mar 14, 2021 4:36 pm

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316 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:36 pm
The PN Generator reset port must be of type boolean.

Last post by omidrostaei « Sun Mar 14, 2021 4:35 pm

by omidrostaei » Sun Mar 14, 2021 4:35 pm

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331 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:35 pm
Initial HDL and simulation outputs will mismatch when ResetType is ''none''. Use the ''IgnoreDataChecking'' flag while g

Last post by omidrostaei « Sun Mar 14, 2021 4:35 pm

by omidrostaei » Sun Mar 14, 2021 4:35 pm

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322 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:35 pm
HDL code generation requires at least 2 rows of interleaving.

Last post by omidrostaei « Sun Mar 14, 2021 4:34 pm

by omidrostaei » Sun Mar 14, 2021 4:34 pm

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312 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:34 pm
Vector inputs and outputs are not supported for HDL code generation.

Last post by omidrostaei « Sun Mar 14, 2021 4:34 pm

by omidrostaei » Sun Mar 14, 2021 4:34 pm

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320 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:34 pm
Non-zero initial conditions are not supported for the RAM based architecture

Last post by omidrostaei « Sun Mar 14, 2021 4:33 pm

by omidrostaei » Sun Mar 14, 2021 4:33 pm

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392 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:33 pm
HDL code generation requires at least 2 rows of interleaving.

Last post by omidrostaei « Sun Mar 14, 2021 4:33 pm

by omidrostaei » Sun Mar 14, 2021 4:33 pm

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289 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:33 pm
The number of RAM locations needed () is less than the minimum supported (N*B*N = ' num2str(minramloc)

Last post by omidrostaei « Sun Mar 14, 2021 4:33 pm

by omidrostaei » Sun Mar 14, 2021 4:33 pm

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340 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:33 pm
Double datatype is not supported for the RAM based architecture

Last post by omidrostaei « Sun Mar 14, 2021 4:33 pm

by omidrostaei » Sun Mar 14, 2021 4:33 pm

0 Replies

327 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:33 pm
Vector inputs and outputs are not supported for HDL code generation.

Last post by omidrostaei « Sun Mar 14, 2021 4:32 pm

by omidrostaei » Sun Mar 14, 2021 4:32 pm

0 Replies

347 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:32 pm
HDL support requires the reset signal to be boolean

Last post by omidrostaei « Sun Mar 14, 2021 4:31 pm

by omidrostaei » Sun Mar 14, 2021 4:31 pm

0 Replies

272 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:31 pm
HDL support requires that the Delay reset action to next time step checkbox be selected. This will lead to a synchronous

Last post by omidrostaei « Sun Mar 14, 2021 4:31 pm

by omidrostaei » Sun Mar 14, 2021 4:31 pm

0 Replies

311 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:31 pm
HDL support requires boolean or ufix1 data input

Last post by omidrostaei « Sun Mar 14, 2021 4:31 pm

by omidrostaei » Sun Mar 14, 2021 4:31 pm

0 Replies

323 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:31 pm
HDL support is not available for the Truncated trellis operation mode

Last post by omidrostaei « Sun Mar 14, 2021 4:30 pm

by omidrostaei » Sun Mar 14, 2021 4:30 pm

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313 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:30 pm
HDL support requires encoding rates from 1/2 to 1/7, or 2/3

Last post by omidrostaei « Sun Mar 14, 2021 4:30 pm

by omidrostaei » Sun Mar 14, 2021 4:30 pm

0 Replies

275 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:30 pm
HDL support requires a constraint length from 3 to 9

Last post by omidrostaei « Sun Mar 14, 2021 4:30 pm

by omidrostaei » Sun Mar 14, 2021 4:30 pm

0 Replies

322 Views

Last post by omidrostaei
Sun Mar 14, 2021 4:30 pm

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