Signal Processing

New Topic

3049 topics

Page 37 of 122
- Jump to page:
Previous
1
…
35
36
37
38
39
…
122
Next

Topics

Replies

Views

Last post

Library must not change. Create a new config object for a different library.

Last post by mamorani « Sat Mar 13, 2021 7:20 pm

by mamorani » Sat Mar 13, 2021 7:20 pm

0 Replies

271 Views

Last post by mamorani
Sat Mar 13, 2021 7:20 pm
Unable to generate IPs to achieve the target frequency

Last post by mamorani « Sat Mar 13, 2021 7:19 pm

by mamorani » Sat Mar 13, 2021 7:19 pm

0 Replies

251 Views

Last post by mamorani
Sat Mar 13, 2021 7:19 pm
A customized latency is set for Some latencies may not be supported by the ALTFP library. Check the ALTFP library doc

Last post by mamorani « Sat Mar 13, 2021 7:19 pm

by mamorani » Sat Mar 13, 2021 7:19 pm

0 Replies

238 Views

Last post by mamorani
Sat Mar 13, 2021 7:19 pm
The simulation compilation scripts may not work properly, because HDL Coder cannot find compiled Altera simulation libra

Last post by mamorani « Sat Mar 13, 2021 7:18 pm

by mamorani » Sat Mar 13, 2021 7:18 pm

0 Replies

241 Views

Last post by mamorani
Sat Mar 13, 2021 7:18 pm
The relational operator mode is unsupported by Altera Megafunction wizard

Last post by mamorani « Sat Mar 13, 2021 7:18 pm

by mamorani » Sat Mar 13, 2021 7:18 pm

0 Replies

266 Views

Last post by mamorani
Sat Mar 13, 2021 7:18 pm
Supported Tool Versions in CustomizeReferenceDesignFcn does not match with Supported Tool Versions in reference design p

Last post by mamorani « Sat Mar 13, 2021 7:17 pm

by mamorani » Sat Mar 13, 2021 7:17 pm

0 Replies

282 Views

Last post by mamorani
Sat Mar 13, 2021 7:17 pm
DisableIPCache" and "IPCacheZipFile" cannot both be set in the same reference design.

Last post by mamorani « Sat Mar 13, 2021 6:58 pm

by mamorani » Sat Mar 13, 2021 6:58 pm

0 Replies

283 Views

Last post by mamorani
Sat Mar 13, 2021 6:58 pm
This IP repository is included as part of the "HDL Verifier Support Package for Intel FPGA Boards". To use this IP repos

Last post by mamorani « Sat Mar 13, 2021 6:58 pm

by mamorani » Sat Mar 13, 2021 6:58 pm

0 Replies

351 Views

Last post by mamorani
Sat Mar 13, 2021 6:58 pm
This IP repository is included as part of the "Computer Vision System Toolbox Support Package for Xilinx Zynq-Based Hard

Last post by mamorani « Sat Mar 13, 2021 6:57 pm

by mamorani » Sat Mar 13, 2021 6:57 pm

0 Replies

255 Views

Last post by mamorani
Sat Mar 13, 2021 6:57 pm
Turn on Insert JTAG MATLAB as AXI Master parameter requires the IP repository function , which cannot be found on t

Last post by mamorani « Sat Mar 13, 2021 6:57 pm

by mamorani » Sat Mar 13, 2021 6:57 pm

0 Replies

304 Views

Last post by mamorani
Sat Mar 13, 2021 6:57 pm
The value specified for ''EmbeddedCoderSupportPackage'' is not a valid enumeration of the class ''hdlcoder.EmbeddedCoder

Last post by mamorani « Sat Mar 13, 2021 6:53 pm

by mamorani » Sat Mar 13, 2021 6:53 pm

0 Replies

280 Views

Last post by mamorani
Sat Mar 13, 2021 6:53 pm
The first output of the board registration file " must be a cell array of character vectors.

Last post by mamorani « Sat Mar 13, 2021 6:51 pm

by mamorani » Sat Mar 13, 2021 6:51 pm

0 Replies

280 Views

Last post by mamorani
Sat Mar 13, 2021 6:51 pm
Too many outputs in the board registration file, " There can be at most two outputs in the board registration file

Last post by mamorani « Sat Mar 13, 2021 6:49 pm

by mamorani » Sat Mar 13, 2021 6:49 pm

0 Replies

253 Views

Last post by mamorani
Sat Mar 13, 2021 6:49 pm
Invalid property value for property Value must be a character vector, and not a cell array of character vectors. For e

Last post by mamorani « Sat Mar 13, 2021 6:49 pm

by mamorani » Sat Mar 13, 2021 6:49 pm

0 Replies

323 Views

Last post by mamorani
Sat Mar 13, 2021 6:49 pm
Reference design name in CustomizeReferenceDesignFcn does not match with reference design name in reference design plug

Last post by mamorani « Sat Mar 13, 2021 6:48 pm

by mamorani » Sat Mar 13, 2021 6:48 pm

0 Replies

292 Views

Last post by mamorani
Sat Mar 13, 2021 6:48 pm
Number of elements specified for 'MasterAddressSpace' and the 'BaseAddress' properties in Plugin_rd.m are unequal. Make

Last post by mamorani « Sat Mar 13, 2021 6:47 pm

by mamorani » Sat Mar 13, 2021 6:47 pm

0 Replies

238 Views

Last post by mamorani
Sat Mar 13, 2021 6:47 pm
Invalid property value for property valid value must be a integer number >= 0, for example,

Last post by mamorani « Sat Mar 13, 2021 6:46 pm

by mamorani » Sat Mar 13, 2021 6:46 pm

0 Replies

251 Views

Last post by mamorani
Sat Mar 13, 2021 6:46 pm
Constructing reference design definition object for tool is not supported, the supported tools are

Last post by mamorani « Sat Mar 13, 2021 6:46 pm

by mamorani » Sat Mar 13, 2021 6:46 pm

0 Replies

268 Views

Last post by mamorani
Sat Mar 13, 2021 6:46 pm
Constructing board definition object for workflow is not supported

Last post by mamorani « Sat Mar 13, 2021 6:45 pm

by mamorani » Sat Mar 13, 2021 6:45 pm

0 Replies

241 Views

Last post by mamorani
Sat Mar 13, 2021 6:45 pm
When ''ParameterType'' is hdlcoder.ParameterType.Dropdown, the value specified for ''Choice'' must be a non-empty cell a

Last post by mamorani « Sat Mar 13, 2021 6:44 pm

by mamorani » Sat Mar 13, 2021 6:44 pm

0 Replies

250 Views

Last post by mamorani
Sat Mar 13, 2021 6:44 pm
Too many outputs in the IP repository function, . There can be at most two outputs in the IP repository function.

Last post by mamorani « Sat Mar 13, 2021 6:44 pm

by mamorani » Sat Mar 13, 2021 6:44 pm

0 Replies

254 Views

Last post by mamorani
Sat Mar 13, 2021 6:44 pm
An InterfaceID can only be specified on a single interface. Please specify the interfaceType as either "AXI4" or "AXI4-L

Last post by mamorani « Sat Mar 13, 2021 6:44 pm

by mamorani » Sat Mar 13, 2021 6:44 pm

0 Replies

243 Views

Last post by mamorani
Sat Mar 13, 2021 6:44 pm
Clock interface must be defined first before running this method. Please use following command to define clock interface

Last post by mamorani « Sat Mar 13, 2021 6:43 pm

by mamorani » Sat Mar 13, 2021 6:43 pm

0 Replies

248 Views

Last post by mamorani
Sat Mar 13, 2021 6:43 pm
Reference design property JTAGAXIMasteroptionVisible's property value must be set to 'false', as the JTAG AXI Master IP

Last post by mamorani « Sat Mar 13, 2021 6:43 pm

by mamorani » Sat Mar 13, 2021 6:43 pm

0 Replies

246 Views

Last post by mamorani
Sat Mar 13, 2021 6:43 pm
Invalid property value for property valid value must be a integer number in the range for example,

Last post by mamorani « Sat Mar 13, 2021 6:42 pm

by mamorani » Sat Mar 13, 2021 6:42 pm

0 Replies

255 Views

Last post by mamorani
Sat Mar 13, 2021 6:42 pm

New Topic

3049 topics

Page 37 of 122
- Jump to page:
Previous
1
…
35
36
37
38
39
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 1 guest

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum