Signal Processing

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Duplicate supported tool version ' are found from two reference design plugins that shares the same name, and ' . Eit

Last post by mamorani « Sat Mar 13, 2021 8:14 pm

by mamorani » Sat Mar 13, 2021 8:14 pm

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Last post by mamorani
Sat Mar 13, 2021 8:14 pm
Duplicate plugin path is found from two registration functions and

Last post by mamorani « Sat Mar 13, 2021 8:13 pm

by mamorani » Sat Mar 13, 2021 8:13 pm

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291 Views

Last post by mamorani
Sat Mar 13, 2021 8:13 pm
Register name is reserved by system, please do not use this name as port name.

Last post by mamorani « Sat Mar 13, 2021 8:13 pm

by mamorani » Sat Mar 13, 2021 8:13 pm

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Last post by mamorani
Sat Mar 13, 2021 8:13 pm
Register name is reserved by system, please do not use this name as port name.

Last post by mamorani « Sat Mar 13, 2021 8:05 pm

by mamorani » Sat Mar 13, 2021 8:05 pm

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314 Views

Last post by mamorani
Sat Mar 13, 2021 8:05 pm
The directory path does not exist from current working directory.

Last post by mamorani « Sat Mar 13, 2021 8:01 pm

by mamorani » Sat Mar 13, 2021 8:01 pm

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366 Views

Last post by mamorani
Sat Mar 13, 2021 8:01 pm
The target workflow requires a Deep Learning reference design.

Last post by mamorani « Sat Mar 13, 2021 8:00 pm

by mamorani » Sat Mar 13, 2021 8:00 pm

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325 Views

Last post by mamorani
Sat Mar 13, 2021 8:00 pm
Error detected in port assignment. This FPGA board requires channel ,number,integer}" and channel " ,number,integer}" to

Last post by mamorani « Sat Mar 13, 2021 7:58 pm

by mamorani » Sat Mar 13, 2021 7:58 pm

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308 Views

Last post by mamorani
Sat Mar 13, 2021 7:58 pm
An existing Xilinx ISE project file was created by a different version of Xilinx ISE. This project file uses the same p

Last post by mamorani « Sat Mar 13, 2021 7:57 pm

by mamorani » Sat Mar 13, 2021 7:57 pm

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297 Views

Last post by mamorani
Sat Mar 13, 2021 7:57 pm
DefaultBusInterface must be assigned in board plugin file for coprocessing mode.

Last post by mamorani « Sat Mar 13, 2021 7:56 pm

by mamorani » Sat Mar 13, 2021 7:56 pm

0 Replies

451 Views

Last post by mamorani
Sat Mar 13, 2021 7:56 pm
Name containing "-" is not supported. Please change your

Last post by mamorani « Sat Mar 13, 2021 7:55 pm

by mamorani » Sat Mar 13, 2021 7:55 pm

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424 Views

Last post by mamorani
Sat Mar 13, 2021 7:55 pm
Interface is not supported in mode, please use mode instead.

Last post by mamorani « Sat Mar 13, 2021 7:51 pm

by mamorani » Sat Mar 13, 2021 7:51 pm

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270 Views

Last post by mamorani
Sat Mar 13, 2021 7:51 pm
This workflow requires Communications Toolbox. Make sure that Communications Toolbox is licensed and installed

Last post by mamorani « Sat Mar 13, 2021 7:50 pm

by mamorani » Sat Mar 13, 2021 7:50 pm

0 Replies

315 Views

Last post by mamorani
Sat Mar 13, 2021 7:50 pm
Downstream Integration: HDLCoder code generation must complete successfully prior to running Downstream Tool Integration

Last post by mamorani « Sat Mar 13, 2021 7:50 pm

by mamorani » Sat Mar 13, 2021 7:50 pm

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326 Views

Last post by mamorani
Sat Mar 13, 2021 7:50 pm
Switching Processor/FPGA synchronization mode to causes incompatible interface assignment on following ports. The inte

Last post by mamorani « Sat Mar 13, 2021 7:50 pm

by mamorani » Sat Mar 13, 2021 7:50 pm

0 Replies

264 Views

Last post by mamorani
Sat Mar 13, 2021 7:50 pm
Attempt to automatically assign interface for coprocessing modes is not successful on following ports:

Last post by mamorani « Sat Mar 13, 2021 7:49 pm

by mamorani » Sat Mar 13, 2021 7:49 pm

0 Replies

433 Views

Last post by mamorani
Sat Mar 13, 2021 7:49 pm
port have Bus data type. Bus data type not supported for test points.

Last post by mamorani « Sat Mar 13, 2021 7:48 pm

by mamorani » Sat Mar 13, 2021 7:48 pm

0 Replies

285 Views

Last post by mamorani
Sat Mar 13, 2021 7:48 pm
Build FPGA Bitstream" unsuccessful. See log for details

Last post by mamorani « Sat Mar 13, 2021 7:48 pm

by mamorani » Sat Mar 13, 2021 7:48 pm

0 Replies

268 Views

Last post by mamorani
Sat Mar 13, 2021 7:48 pm
Bit range input is not supported for Target Interface

Last post by mamorani « Sat Mar 13, 2021 7:47 pm

by mamorani » Sat Mar 13, 2021 7:47 pm

0 Replies

338 Views

Last post by mamorani
Sat Mar 13, 2021 7:47 pm
Bit packing on comp ' is not supported when input/output wordlength is not integer multiple of each other

Last post by mamorani « Sat Mar 13, 2021 7:47 pm

by mamorani » Sat Mar 13, 2021 7:47 pm

0 Replies

280 Views

Last post by mamorani
Sat Mar 13, 2021 7:47 pm
Interface only supports port with bit width equal to 32 bits, please change port to 32 bits

Last post by mamorani « Sat Mar 13, 2021 7:47 pm

by mamorani » Sat Mar 13, 2021 7:47 pm

0 Replies

351 Views

Last post by mamorani
Sat Mar 13, 2021 7:47 pm
Vector size mismatch is detected during model generation of bit packing subsystem.

Last post by mamorani « Sat Mar 13, 2021 7:46 pm

by mamorani » Sat Mar 13, 2021 7:46 pm

0 Replies

341 Views

Last post by mamorani
Sat Mar 13, 2021 7:46 pm
Bidirectional INOUT ports are only supported with External Port interface in IP Core Generation workflow, it is not supp

Last post by mamorani « Sat Mar 13, 2021 7:45 pm

by mamorani » Sat Mar 13, 2021 7:45 pm

0 Replies

270 Views

Last post by mamorani
Sat Mar 13, 2021 7:45 pm
IP Core Generation workflow requires the starting subsystem to be an atomic subsystem. Please click the following link

Last post by mamorani « Sat Mar 13, 2021 7:44 pm

by mamorani » Sat Mar 13, 2021 7:44 pm

0 Replies

374 Views

Last post by mamorani
Sat Mar 13, 2021 7:44 pm
Error in applying model''s target hardware settings in the HDL Workflow Advisor.\n Please see the Diagnostic Viewer for

Last post by mamorani « Sat Mar 13, 2021 7:40 pm

by mamorani » Sat Mar 13, 2021 7:40 pm

0 Replies

562 Views

Last post by mamorani
Sat Mar 13, 2021 7:40 pm
Failed to apply model's reference design settings in task Set Target Interface in the HDL Workflow Advisor for the follo

Last post by mamorani « Sat Mar 13, 2021 7:39 pm

by mamorani » Sat Mar 13, 2021 7:39 pm

0 Replies

543 Views

Last post by mamorani
Sat Mar 13, 2021 7:39 pm

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