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Port Name of block is not registered in Target Interface Table

Last post by mamorani « Sat Mar 13, 2021 8:37 pm

by mamorani » Sat Mar 13, 2021 8:37 pm

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441 Views

Last post by mamorani
Sat Mar 13, 2021 8:37 pm
Invalid input for The minimum value that can be assigned is and the maximum value is

Last post by mamorani « Sat Mar 13, 2021 8:35 pm

by mamorani » Sat Mar 13, 2021 8:35 pm

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337 Views

Last post by mamorani
Sat Mar 13, 2021 8:35 pm
Downstream Integration: Unable to read family data from XML file

Last post by mamorani « Sat Mar 13, 2021 8:34 pm

by mamorani » Sat Mar 13, 2021 8:34 pm

0 Replies

311 Views

Last post by mamorani
Sat Mar 13, 2021 8:34 pm
Additional source file does not exist.\nPlease use Add... button to add additional source file,\nor type the file path

Last post by mamorani « Sat Mar 13, 2021 8:34 pm

by mamorani » Sat Mar 13, 2021 8:34 pm

0 Replies

308 Views

Last post by mamorani
Sat Mar 13, 2021 8:34 pm
Invalid address offset input valid address should be multiple of 4.

Last post by mamorani « Sat Mar 13, 2021 8:33 pm

by mamorani » Sat Mar 13, 2021 8:33 pm

0 Replies

317 Views

Last post by mamorani
Sat Mar 13, 2021 8:33 pm
Getting bit range index is not supported for interface please get bit range directly

Last post by mamorani « Sat Mar 13, 2021 8:33 pm

by mamorani » Sat Mar 13, 2021 8:33 pm

0 Replies

283 Views

Last post by mamorani
Sat Mar 13, 2021 8:33 pm
ID Width value must be an integer greater than 0 and less than 129.

Last post by mamorani « Sat Mar 13, 2021 8:32 pm

by mamorani » Sat Mar 13, 2021 8:32 pm

0 Replies

280 Views

Last post by mamorani
Sat Mar 13, 2021 8:32 pm
should only be used in IP Core Generation workflow.

Last post by mamorani « Sat Mar 13, 2021 8:31 pm

by mamorani » Sat Mar 13, 2021 8:31 pm

0 Replies

324 Views

Last post by mamorani
Sat Mar 13, 2021 8:31 pm
The IP core name conflicts with DUT HDL file name, please change the IP core name

Last post by mamorani « Sat Mar 13, 2021 8:29 pm

by mamorani » Sat Mar 13, 2021 8:29 pm

0 Replies

342 Views

Last post by mamorani
Sat Mar 13, 2021 8:29 pm
The IP core "Additional source file" name conflicts with the generated IP core HDL file name, please change the additio

Last post by mamorani « Sat Mar 13, 2021 8:28 pm

by mamorani » Sat Mar 13, 2021 8:28 pm

0 Replies

394 Views

Last post by mamorani
Sat Mar 13, 2021 8:28 pm
IP core generation only support file as additional source file when HDL code generation Target Language setting is is

Last post by mamorani « Sat Mar 13, 2021 8:22 pm

by mamorani » Sat Mar 13, 2021 8:22 pm

0 Replies

341 Views

Last post by mamorani
Sat Mar 13, 2021 8:22 pm
is adjusted automatically in order to accommodate the MATLAB as AXI Master IP in reference designs. Also there is an opt

Last post by mamorani « Sat Mar 13, 2021 8:21 pm

by mamorani » Sat Mar 13, 2021 8:21 pm

0 Replies

292 Views

Last post by mamorani
Sat Mar 13, 2021 8:21 pm
Model name or DUT subsystem name must be ASCII compliant. Please update your DUT subsystem name

Last post by mamorani « Sat Mar 13, 2021 8:20 pm

by mamorani » Sat Mar 13, 2021 8:20 pm

0 Replies

357 Views

Last post by mamorani
Sat Mar 13, 2021 8:20 pm
must be ASCII compliant. Please change your input

Last post by mamorani « Sat Mar 13, 2021 8:19 pm

by mamorani » Sat Mar 13, 2021 8:19 pm

0 Replies

346 Views

Last post by mamorani
Sat Mar 13, 2021 8:19 pm
Generate a software interface model with IP core driver blocks for C code generation

Last post by mamorani « Sat Mar 13, 2021 8:19 pm

by mamorani » Sat Mar 13, 2021 8:19 pm

0 Replies

343 Views

Last post by mamorani
Sat Mar 13, 2021 8:19 pm
Select to add the device driver for your generated IP core to the onboard Linux kernel and reboot Linux

Last post by mamorani « Sat Mar 13, 2021 8:19 pm

by mamorani » Sat Mar 13, 2021 8:19 pm

0 Replies

303 Views

Last post by mamorani
Sat Mar 13, 2021 8:19 pm
Please make sure HDL Coder Support Package for Intel SoC Devices is installed

Last post by mamorani « Sat Mar 13, 2021 8:18 pm

by mamorani » Sat Mar 13, 2021 8:18 pm

0 Replies

328 Views

Last post by mamorani
Sat Mar 13, 2021 8:18 pm
FPGA Pin input with size ,number,integer} does not match with port with bit width number,integer}

Last post by mamorani « Sat Mar 13, 2021 8:17 pm

by mamorani » Sat Mar 13, 2021 8:17 pm

0 Replies

357 Views

Last post by mamorani
Sat Mar 13, 2021 8:17 pm
'Run build process externally'' must be unchecked or ''RunExternalBuild'' must be set to ''false'' for this reference de

Last post by mamorani « Sat Mar 13, 2021 8:17 pm

by mamorani » Sat Mar 13, 2021 8:17 pm

0 Replies

303 Views

Last post by mamorani
Sat Mar 13, 2021 8:17 pm
Programming done. The system will now reboot for persistent changes to take effect.

Last post by mamorani « Sat Mar 13, 2021 8:16 pm

by mamorani » Sat Mar 13, 2021 8:16 pm

0 Replies

365 Views

Last post by mamorani
Sat Mar 13, 2021 8:16 pm
Downloading target FPGA device configuration over Ethernet to SD card ...

Last post by mamorani « Sat Mar 13, 2021 8:15 pm

by mamorani » Sat Mar 13, 2021 8:15 pm

0 Replies

328 Views

Last post by mamorani
Sat Mar 13, 2021 8:15 pm
Synthesis tool is not available on specified tool path in plug-in file.

Last post by mamorani « Sat Mar 13, 2021 8:15 pm

by mamorani » Sat Mar 13, 2021 8:15 pm

0 Replies

318 Views

Last post by mamorani
Sat Mar 13, 2021 8:15 pm
To use the Ethernet FPGA Programming method, must be installed.

Last post by mamorani « Sat Mar 13, 2021 8:15 pm

by mamorani » Sat Mar 13, 2021 8:15 pm

0 Replies

308 Views

Last post by mamorani
Sat Mar 13, 2021 8:15 pm
is not installed. It is required in order to run task "

Last post by mamorani « Sat Mar 13, 2021 8:14 pm

by mamorani » Sat Mar 13, 2021 8:14 pm

0 Replies

326 Views

Last post by mamorani
Sat Mar 13, 2021 8:14 pm
Embedded Coder is not licensed or installed. Please make sure Embedded Coder is licensed and installed in order to run t

Last post by mamorani « Sat Mar 13, 2021 8:14 pm

by mamorani » Sat Mar 13, 2021 8:14 pm

0 Replies

310 Views

Last post by mamorani
Sat Mar 13, 2021 8:14 pm

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