Signal Processing

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Streaming interface need to be assigned in pair, both and " interfaces need to be assigned

Last post by mamorani « Sat Mar 13, 2021 9:03 pm

by mamorani » Sat Mar 13, 2021 9:03 pm

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Last post by mamorani
Sat Mar 13, 2021 9:03 pm
Streaming interface is not supported in mode, please use mode for streaming interface

Last post by mamorani « Sat Mar 13, 2021 9:02 pm

by mamorani » Sat Mar 13, 2021 9:02 pm

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274 Views

Last post by mamorani
Sat Mar 13, 2021 9:02 pm
IP Core name cannot begin/end in an underscore and cannot contain multiple contiguous underscore characters. Please chan

Last post by mamorani « Sat Mar 13, 2021 9:02 pm

by mamorani » Sat Mar 13, 2021 9:02 pm

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293 Views

Last post by mamorani
Sat Mar 13, 2021 9:02 pm
Name containing white space is not supported. Please change your

Last post by mamorani « Sat Mar 13, 2021 9:01 pm

by mamorani » Sat Mar 13, 2021 9:01 pm

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290 Views

Last post by mamorani
Sat Mar 13, 2021 9:01 pm
Path containing white space is not supported. Please change your

Last post by mamorani « Sat Mar 13, 2021 8:59 pm

by mamorani » Sat Mar 13, 2021 8:59 pm

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270 Views

Last post by mamorani
Sat Mar 13, 2021 8:59 pm
Following are the previously generated FPGA top level wrapper files

Last post by mamorani « Sat Mar 13, 2021 8:59 pm

by mamorani » Sat Mar 13, 2021 8:59 pm

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277 Views

Last post by mamorani
Sat Mar 13, 2021 8:59 pm
Skipped the task because no functional changes were found. \n To force rebuild, click and run this task again

Last post by mamorani « Sat Mar 13, 2021 8:58 pm

by mamorani » Sat Mar 13, 2021 8:58 pm

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306 Views

Last post by mamorani
Sat Mar 13, 2021 8:58 pm
Unable to connect internal signal because of signal type mismatch

Last post by mamorani « Sat Mar 13, 2021 8:58 pm

by mamorani » Sat Mar 13, 2021 8:58 pm

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315 Views

Last post by mamorani
Sat Mar 13, 2021 8:58 pm
Shift register address decoder does not support scalar data type in turnkey code generation

Last post by mamorani « Sat Mar 13, 2021 8:57 pm

by mamorani » Sat Mar 13, 2021 8:57 pm

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305 Views

Last post by mamorani
Sat Mar 13, 2021 8:57 pm
You can use the hdlsetuptoolpath function to add the appropriate synthesis tool path to your system path for the current

Last post by mamorani « Sat Mar 13, 2021 8:57 pm

by mamorani » Sat Mar 13, 2021 8:57 pm

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291 Views

Last post by mamorani
Sat Mar 13, 2021 8:57 pm
Cancelled To pass this task without running , deselect this option and run this task again

Last post by mamorani « Sat Mar 13, 2021 8:56 pm

by mamorani » Sat Mar 13, 2021 8:56 pm

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269 Views

Last post by mamorani
Sat Mar 13, 2021 8:56 pm
Generated software interface script file(s) already exist in the current directory. Would you like to overwrite these

Last post by mamorani « Sat Mar 13, 2021 8:56 pm

by mamorani » Sat Mar 13, 2021 8:56 pm

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279 Views

Last post by mamorani
Sat Mar 13, 2021 8:56 pm
The use of the legacy SDR workflow is not supported.

Last post by mamorani « Sat Mar 13, 2021 8:55 pm

by mamorani » Sat Mar 13, 2021 8:55 pm

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311 Views

Last post by mamorani
Sat Mar 13, 2021 8:55 pm
This workflow requires MATLAB and Simulink Support Package for SDR devices. For more information, see https://www.mathwo

Last post by mamorani « Sat Mar 13, 2021 8:54 pm

by mamorani » Sat Mar 13, 2021 8:54 pm

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263 Views

Last post by mamorani
Sat Mar 13, 2021 8:54 pm
For more advice on how to resolve timing failure, please follow the and also read the for details

Last post by mamorani « Sat Mar 13, 2021 8:54 pm

by mamorani » Sat Mar 13, 2021 8:54 pm

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298 Views

Last post by mamorani
Sat Mar 13, 2021 8:54 pm
The system build has been launched in an external shell, please check the external console to make sure the bitstream ge

Last post by mamorani « Sat Mar 13, 2021 8:53 pm

by mamorani » Sat Mar 13, 2021 8:53 pm

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339 Views

Last post by mamorani
Sat Mar 13, 2021 8:53 pm
Please check the external console to make sure the bitstream generation is completed and try again.

Last post by mamorani « Sat Mar 13, 2021 8:53 pm

by mamorani » Sat Mar 13, 2021 8:53 pm

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276 Views

Last post by mamorani
Sat Mar 13, 2021 8:53 pm
The HDL Workflow Advisor does not support the resettable timing controller architecture.

Last post by mamorani « Sat Mar 13, 2021 8:53 pm

by mamorani » Sat Mar 13, 2021 8:53 pm

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359 Views

Last post by mamorani
Sat Mar 13, 2021 8:53 pm
The reference design in folder is not version

Last post by mamorani « Sat Mar 13, 2021 8:52 pm

by mamorani » Sat Mar 13, 2021 8:52 pm

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273 Views

Last post by mamorani
Sat Mar 13, 2021 8:52 pm
In order to create project targeting reference design please and specify the path to the reference design in the "Ref

Last post by mamorani « Sat Mar 13, 2021 8:52 pm

by mamorani » Sat Mar 13, 2021 8:52 pm

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281 Views

Last post by mamorani
Sat Mar 13, 2021 8:52 pm
is not a valid reference design folder, please specify the path to the reference design top level which contain "boot_im

Last post by mamorani « Sat Mar 13, 2021 8:52 pm

by mamorani » Sat Mar 13, 2021 8:52 pm

0 Replies

283 Views

Last post by mamorani
Sat Mar 13, 2021 8:52 pm
Downstream Integration: Please first create synthesis tool project file before attempt to open target tool.

Last post by mamorani « Sat Mar 13, 2021 8:51 pm

by mamorani » Sat Mar 13, 2021 8:51 pm

0 Replies

286 Views

Last post by mamorani
Sat Mar 13, 2021 8:51 pm
Bit range input out of support bit range number,integer}] of interface with bit-width number,integer}

Last post by mamorani « Sat Mar 13, 2021 8:51 pm

by mamorani » Sat Mar 13, 2021 8:51 pm

0 Replies

282 Views

Last post by mamorani
Sat Mar 13, 2021 8:51 pm
Interface requires bit range input to be one channel only.

Last post by mamorani « Sat Mar 13, 2021 8:50 pm

by mamorani » Sat Mar 13, 2021 8:50 pm

0 Replies

293 Views

Last post by mamorani
Sat Mar 13, 2021 8:50 pm
Simulink Real-Time Interface Model Generation is not supported for current board

Last post by mamorani « Sat Mar 13, 2021 8:49 pm

by mamorani » Sat Mar 13, 2021 8:49 pm

0 Replies

304 Views

Last post by mamorani
Sat Mar 13, 2021 8:49 pm

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