Signal Processing

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The Design has ports with data type on Please update the port data type or select the appropriate Floating Point Lib

Last post by mamorani « Sat Mar 13, 2021 9:22 pm

by mamorani » Sat Mar 13, 2021 9:22 pm

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260 Views

Last post by mamorani
Sat Mar 13, 2021 9:22 pm
Script generation is not supported when using Coprocessing mode. Please uncheck and rerun this task

Last post by mamorani « Sat Mar 13, 2021 9:22 pm

by mamorani » Sat Mar 13, 2021 9:22 pm

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251 Views

Last post by mamorani
Sat Mar 13, 2021 9:22 pm
Do not support adding block in Simulink Real-Time Model Generation

Last post by mamorani « Sat Mar 13, 2021 9:21 pm

by mamorani » Sat Mar 13, 2021 9:21 pm

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269 Views

Last post by mamorani
Sat Mar 13, 2021 9:21 pm
IP Core Generation/FPGA Turnkey workflows do not support structures at the interface. Found unsupported structure variab

Last post by mamorani « Sat Mar 13, 2021 9:21 pm

by mamorani » Sat Mar 13, 2021 9:21 pm

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337 Views

Last post by mamorani
Sat Mar 13, 2021 9:21 pm
Unsupported HDL file extension is detected on file please check the HDL file extension settings

Last post by mamorani « Sat Mar 13, 2021 9:20 pm

by mamorani » Sat Mar 13, 2021 9:20 pm

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318 Views

Last post by mamorani
Sat Mar 13, 2021 9:20 pm
The FPGA device used in is not supported by your current synthesis tool,

Last post by mamorani « Sat Mar 13, 2021 9:20 pm

by mamorani » Sat Mar 13, 2021 9:20 pm

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327 Views

Last post by mamorani
Sat Mar 13, 2021 9:20 pm
Unable to create directory please check write permission.

Last post by mamorani « Sat Mar 13, 2021 9:18 pm

by mamorani » Sat Mar 13, 2021 9:18 pm

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248 Views

Last post by mamorani
Sat Mar 13, 2021 9:18 pm
Unable to create iMPACT batch file ,please check write permission

Last post by mamorani « Sat Mar 13, 2021 9:18 pm

by mamorani » Sat Mar 13, 2021 9:18 pm

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250 Views

Last post by mamorani
Sat Mar 13, 2021 9:18 pm
need to send software reset to clock module, please specify ''InternalReset'' option in clock module

Last post by mamorani « Sat Mar 13, 2021 9:17 pm

by mamorani » Sat Mar 13, 2021 9:17 pm

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262 Views

Last post by mamorani
Sat Mar 13, 2021 9:17 pm
This workflow requires MATLAB and Simulink Support Package for USRP(R) devices. This package is available for download a

Last post by mamorani « Sat Mar 13, 2021 9:17 pm

by mamorani » Sat Mar 13, 2021 9:17 pm

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305 Views

Last post by mamorani
Sat Mar 13, 2021 9:17 pm
UNC toolpath is not supported for . Please map your UNC toolpath to a network drive and try again

Last post by mamorani « Sat Mar 13, 2021 9:17 pm

by mamorani » Sat Mar 13, 2021 9:17 pm

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258 Views

Last post by mamorani
Sat Mar 13, 2021 9:17 pm
UNC path is not supported. Please change your " path

Last post by mamorani « Sat Mar 13, 2021 9:16 pm

by mamorani » Sat Mar 13, 2021 9:16 pm

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297 Views

Last post by mamorani
Sat Mar 13, 2021 9:16 pm
The ''Scalarize ports'' option must be set as ''dutlevel'' when there is a vector port on the DUT interface. Please clic

Last post by mamorani « Sat Mar 13, 2021 9:11 pm

by mamorani » Sat Mar 13, 2021 9:11 pm

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315 Views

Last post by mamorani
Sat Mar 13, 2021 9:11 pm
The ''Generate HDL Code'' option in the Configuration Parameters dialog box must be selected to run this task.

Last post by mamorani « Sat Mar 13, 2021 9:11 pm

by mamorani » Sat Mar 13, 2021 9:11 pm

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327 Views

Last post by mamorani
Sat Mar 13, 2021 9:11 pm
As the JTAG AXI Master IP is already present in this reference design. Reference design parameter "insert JTAG MATLAB as

Last post by mamorani « Sat Mar 13, 2021 9:10 pm

by mamorani » Sat Mar 13, 2021 9:10 pm

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319 Views

Last post by mamorani
Sat Mar 13, 2021 9:10 pm
Target platform requires one of the following synthesis tools However, none of these tools are available on the system

Last post by mamorani « Sat Mar 13, 2021 9:10 pm

by mamorani » Sat Mar 13, 2021 9:10 pm

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282 Views

Last post by mamorani
Sat Mar 13, 2021 9:10 pm
Selected synthesis tool is not available on the system path. Available tools are

Last post by mamorani « Sat Mar 13, 2021 9:09 pm

by mamorani » Sat Mar 13, 2021 9:09 pm

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243 Views

Last post by mamorani
Sat Mar 13, 2021 9:09 pm
auto-generate unique names for all test points in the system

Last post by mamorani « Sat Mar 13, 2021 9:09 pm

by mamorani » Sat Mar 13, 2021 9:09 pm

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269 Views

Last post by mamorani
Sat Mar 13, 2021 9:09 pm
Test points with unspecified or duplicate names present in the system. Click to

Last post by mamorani « Sat Mar 13, 2021 9:08 pm

by mamorani » Sat Mar 13, 2021 9:08 pm

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273 Views

Last post by mamorani
Sat Mar 13, 2021 9:08 pm
Model inport outport number mismatch with last stored Target Interface Table

Last post by mamorani « Sat Mar 13, 2021 9:08 pm

by mamorani » Sat Mar 13, 2021 9:08 pm

0 Replies

301 Views

Last post by mamorani
Sat Mar 13, 2021 9:08 pm
Port data type of port has been changed from to since last stored Target Interface Table

Last post by mamorani « Sat Mar 13, 2021 9:07 pm

by mamorani » Sat Mar 13, 2021 9:07 pm

0 Replies

266 Views

Last post by mamorani
Sat Mar 13, 2021 9:07 pm
Downstream Integration: Synthesis tool is not specified.

Last post by mamorani « Sat Mar 13, 2021 9:07 pm

by mamorani » Sat Mar 13, 2021 9:07 pm

0 Replies

283 Views

Last post by mamorani
Sat Mar 13, 2021 9:07 pm
is not installed, which may be required to run task It is recommended to complete the installation before proceeding.

Last post by mamorani « Sat Mar 13, 2021 9:06 pm

by mamorani » Sat Mar 13, 2021 9:06 pm

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257 Views

Last post by mamorani
Sat Mar 13, 2021 9:06 pm
treaming interface requires all input and output ports uses the same sample rate, please check the sample rate for port

Last post by mamorani « Sat Mar 13, 2021 9:04 pm

by mamorani » Sat Mar 13, 2021 9:04 pm

0 Replies

437 Views

Last post by mamorani
Sat Mar 13, 2021 9:04 pm
More than two streaming interface is not supported.

Last post by mamorani « Sat Mar 13, 2021 9:03 pm

by mamorani » Sat Mar 13, 2021 9:03 pm

0 Replies

251 Views

Last post by mamorani
Sat Mar 13, 2021 9:03 pm

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