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No test bench stimulus was specified, using the default stimulus for this filter structure

Last post by mamorani « Sat Mar 13, 2021 9:45 pm

by mamorani » Sat Mar 13, 2021 9:45 pm

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304 Views

Last post by mamorani
Sat Mar 13, 2021 9:45 pm
HDL CodeGen Properties is empty, using default values

Last post by mamorani « Sat Mar 13, 2021 9:45 pm

by mamorani » Sat Mar 13, 2021 9:45 pm

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260 Views

Last post by mamorani
Sat Mar 13, 2021 9:45 pm
HDL Testbench generation for this object class is not supported

Last post by mamorani « Sat Mar 13, 2021 9:45 pm

by mamorani » Sat Mar 13, 2021 9:45 pm

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291 Views

Last post by mamorani
Sat Mar 13, 2021 9:45 pm
Unable to check out a license for the Filter Design HDL Coder

Last post by mamorani « Sat Mar 13, 2021 9:44 pm

by mamorani » Sat Mar 13, 2021 9:44 pm

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256 Views

Last post by mamorani
Sat Mar 13, 2021 9:44 pm
FIR interpolation mode of Variable Fractional Delay is not supported for HDL

Last post by mamorani « Sat Mar 13, 2021 9:43 pm

by mamorani » Sat Mar 13, 2021 9:43 pm

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268 Views

Last post by mamorani
Sat Mar 13, 2021 9:43 pm
Internal Error: Unsupported filter structure for System object

Last post by mamorani « Sat Mar 13, 2021 9:43 pm

by mamorani » Sat Mar 13, 2021 9:43 pm

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276 Views

Last post by mamorani
Sat Mar 13, 2021 9:43 pm
Generate HDL from Filter Builder for dsp.FilterCascade based designs is not supported. Instead, use generatehdl in MATLA

Last post by mamorani « Sat Mar 13, 2021 9:42 pm

by mamorani » Sat Mar 13, 2021 9:42 pm

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270 Views

Last post by mamorani
Sat Mar 13, 2021 9:42 pm
The current synthesis tool does not support IP caching. To use IP caching, you must use "Xilinx Vivado 2015.4" or newe

Last post by mamorani « Sat Mar 13, 2021 9:40 pm

by mamorani » Sat Mar 13, 2021 9:40 pm

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252 Views

Last post by mamorani
Sat Mar 13, 2021 9:40 pm
The reference design has disabled the use of Out-Of-Context (OOC) synthesis which requires "Enable IP Caching" to be s

Last post by mamorani « Sat Mar 13, 2021 9:39 pm

by mamorani » Sat Mar 13, 2021 9:39 pm

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268 Views

Last post by mamorani
Sat Mar 13, 2021 9:39 pm
The reference design contains an IP cache repository. Setting "Enable IP Caching" to "false" may result in slower synt

Last post by mamorani « Sat Mar 13, 2021 9:38 pm

by mamorani » Sat Mar 13, 2021 9:38 pm

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260 Views

Last post by mamorani
Sat Mar 13, 2021 9:38 pm
FPGA targeting for the USRP N210 platform will be removed in a future release

Last post by mamorani « Sat Mar 13, 2021 9:37 pm

by mamorani » Sat Mar 13, 2021 9:37 pm

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253 Views

Last post by mamorani
Sat Mar 13, 2021 9:37 pm
The board post model generation callback returned a failing status:

Last post by mamorani « Sat Mar 13, 2021 9:37 pm

by mamorani » Sat Mar 13, 2021 9:37 pm

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269 Views

Last post by mamorani
Sat Mar 13, 2021 9:37 pm
The reference design post model generation callback returned a failing status:

Last post by mamorani « Sat Mar 13, 2021 9:36 pm

by mamorani » Sat Mar 13, 2021 9:36 pm

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275 Views

Last post by mamorani
Sat Mar 13, 2021 9:36 pm
Generate an HDL Workflow Command-Line Interface script to program the target device

Last post by mamorani « Sat Mar 13, 2021 9:36 pm

by mamorani » Sat Mar 13, 2021 9:36 pm

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274 Views

Last post by mamorani
Sat Mar 13, 2021 9:36 pm
Simulink Real-Time is not licensed or installed. Please make sure Simulink Real-Time is licensed and installed in order

Last post by mamorani « Sat Mar 13, 2021 9:36 pm

by mamorani » Sat Mar 13, 2021 9:36 pm

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237 Views

Last post by mamorani
Sat Mar 13, 2021 9:36 pm
go to Xilinx website click the link and download the reference design extract the package

Last post by mamorani « Sat Mar 13, 2021 9:35 pm

by mamorani » Sat Mar 13, 2021 9:35 pm

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280 Views

Last post by mamorani
Sat Mar 13, 2021 9:35 pm
Xilinx IP core version need to be in the format of "vd.dd.c", for example, "v1.00.a"

Last post by mamorani « Sat Mar 13, 2021 9:34 pm

by mamorani » Sat Mar 13, 2021 9:34 pm

0 Replies

277 Views

Last post by mamorani
Sat Mar 13, 2021 9:34 pm
Upper case characters are not allowed in Xilinx IP core name.

Last post by mamorani « Sat Mar 13, 2021 9:34 pm

by mamorani » Sat Mar 13, 2021 9:34 pm

0 Replies

262 Views

Last post by mamorani
Sat Mar 13, 2021 9:34 pm
The generated interface HDL file name conflicts with DUT HDL file name, please set the "Module name prefix" option to

Last post by mamorani « Sat Mar 13, 2021 9:33 pm

by mamorani » Sat Mar 13, 2021 9:33 pm

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282 Views

Last post by mamorani
Sat Mar 13, 2021 9:33 pm
This design does not meet all timing constraints. Please check PAR report for details.

Last post by mamorani « Sat Mar 13, 2021 9:26 pm

by mamorani » Sat Mar 13, 2021 9:26 pm

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288 Views

Last post by mamorani
Sat Mar 13, 2021 9:26 pm
Vector port dimension mismatches with signal dimension in address decoder elaboration phase for comp

Last post by mamorani « Sat Mar 13, 2021 9:25 pm

by mamorani » Sat Mar 13, 2021 9:25 pm

0 Replies

276 Views

Last post by mamorani
Sat Mar 13, 2021 9:25 pm
Interface does not support vector data type on port that has flattened bit-width larger than 1024 Bits

Last post by mamorani « Sat Mar 13, 2021 9:25 pm

by mamorani » Sat Mar 13, 2021 9:25 pm

0 Replies

243 Views

Last post by mamorani
Sat Mar 13, 2021 9:25 pm
Address for vector port must start from the boundary of an address block (integer multiple of a power of two number), fo

Last post by mamorani « Sat Mar 13, 2021 9:24 pm

by mamorani » Sat Mar 13, 2021 9:24 pm

0 Replies

313 Views

Last post by mamorani
Sat Mar 13, 2021 9:24 pm
Floating point data types are not supported on IP core wrapper ports. Please update the port data type on

Last post by mamorani « Sat Mar 13, 2021 9:23 pm

by mamorani » Sat Mar 13, 2021 9:23 pm

0 Replies

352 Views

Last post by mamorani
Sat Mar 13, 2021 9:23 pm
xPC Board " is not supported in MLHDLC Turnkey workflow.

Last post by mamorani « Sat Mar 13, 2021 9:23 pm

by mamorani » Sat Mar 13, 2021 9:23 pm

0 Replies

242 Views

Last post by mamorani
Sat Mar 13, 2021 9:23 pm

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