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Received error: You must manually make the files writable.

Last post by mamorani « Sat Mar 13, 2021 10:25 pm

by mamorani » Sat Mar 13, 2021 10:25 pm

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Last post by mamorani
Sat Mar 13, 2021 10:25 pm
Frame size should be greater than number of flipped bits. See scramblerflip.m for more details

Last post by mamorani « Sat Mar 13, 2021 10:25 pm

by mamorani » Sat Mar 13, 2021 10:25 pm

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295 Views

Last post by mamorani
Sat Mar 13, 2021 10:25 pm
Failed to list the content of design library "work":

Last post by mamorani « Sat Mar 13, 2021 10:24 pm

by mamorani » Sat Mar 13, 2021 10:24 pm

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414 Views

Last post by mamorani
Sat Mar 13, 2021 10:24 pm
Failed to compile HDL files with the following message

Last post by mamorani « Sat Mar 13, 2021 10:23 pm

by mamorani » Sat Mar 13, 2021 10:23 pm

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447 Views

Last post by mamorani
Sat Mar 13, 2021 10:23 pm
The fraction length of port is not a valid number

Last post by mamorani « Sat Mar 13, 2021 10:23 pm

by mamorani » Sat Mar 13, 2021 10:23 pm

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431 Views

Last post by mamorani
Sat Mar 13, 2021 10:23 pm
HDL cosimulation with Simulink requires Simulink license

Last post by mamorani « Sat Mar 13, 2021 10:22 pm

by mamorani » Sat Mar 13, 2021 10:22 pm

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344 Views

Last post by mamorani
Sat Mar 13, 2021 10:22 pm
is not a valid directory. Specify the directory where HDL simulator executables are installed

Last post by mamorani « Sat Mar 13, 2021 10:22 pm

by mamorani » Sat Mar 13, 2021 10:22 pm

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346 Views

Last post by mamorani
Sat Mar 13, 2021 10:22 pm
No MATLAB callback function was scheduled. Please add at least one MATLAB callback function.

Last post by mamorani « Sat Mar 13, 2021 10:22 pm

by mamorani » Sat Mar 13, 2021 10:22 pm

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389 Views

Last post by mamorani
Sat Mar 13, 2021 10:22 pm
Failed to create file in the current directory with the following error message

Last post by mamorani « Sat Mar 13, 2021 10:21 pm

by mamorani » Sat Mar 13, 2021 10:21 pm

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367 Views

Last post by mamorani
Sat Mar 13, 2021 10:21 pm
The specified HDL time is finer than the time resolution in HDL simulator second). It will be truncated by the HDL si

Last post by mamorani « Sat Mar 13, 2021 10:21 pm

by mamorani » Sat Mar 13, 2021 10:21 pm

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381 Views

Last post by mamorani
Sat Mar 13, 2021 10:21 pm
Time-out occurred during launching HDL simulator. Please check the HDL simulator log for error messages.

Last post by mamorani « Sat Mar 13, 2021 10:20 pm

by mamorani » Sat Mar 13, 2021 10:20 pm

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514 Views

Last post by mamorani
Sat Mar 13, 2021 10:20 pm
Could not find HDL simulator executable on your system path. Please specify the HDL simulator installation directory

Last post by mamorani « Sat Mar 13, 2021 10:20 pm

by mamorani » Sat Mar 13, 2021 10:20 pm

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494 Views

Last post by mamorani
Sat Mar 13, 2021 10:20 pm
Could not find constructor with given signature for ClockRowSource

Last post by mamorani « Sat Mar 13, 2021 10:19 pm

by mamorani » Sat Mar 13, 2021 10:19 pm

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392 Views

Last post by mamorani
Sat Mar 13, 2021 10:19 pm
Signal names listed across the Ports and Clocks panes must be unique from each other

Last post by mamorani « Sat Mar 13, 2021 10:18 pm

by mamorani » Sat Mar 13, 2021 10:18 pm

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351 Views

Last post by mamorani
Sat Mar 13, 2021 10:18 pm
conflict between number of port paths, modes, times, signs, and/or fraction lengths; attempting to continue...

Last post by mamorani « Sat Mar 13, 2021 10:17 pm

by mamorani » Sat Mar 13, 2021 10:17 pm

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402 Views

Last post by mamorani
Sat Mar 13, 2021 10:17 pm
The timescale that corresponds to your input is:\n\n 1 second in Simulink corresponds to s in the HDL simulator.\n\nWi

Last post by mamorani « Sat Mar 13, 2021 10:16 pm

by mamorani » Sat Mar 13, 2021 10:16 pm

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419 Views

Last post by mamorani
Sat Mar 13, 2021 10:16 pm
The timescale that corresponds to your input is:\n\n 1 second in Simulink corresponds to s in the HDL simulator.\n\nWit

Last post by mamorani « Sat Mar 13, 2021 10:15 pm

by mamorani » Sat Mar 13, 2021 10:15 pm

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402 Views

Last post by mamorani
Sat Mar 13, 2021 10:15 pm
Error Margin not specified; using the default Error Margin of 4 bits

Last post by mamorani « Sat Mar 13, 2021 10:13 pm

by mamorani » Sat Mar 13, 2021 10:13 pm

0 Replies

442 Views

Last post by mamorani
Sat Mar 13, 2021 10:13 pm
HDL optimization may cause small numeric differences that will be flagged as errors when running this testbench

Last post by mamorani « Sat Mar 13, 2021 10:13 pm

by mamorani » Sat Mar 13, 2021 10:13 pm

0 Replies

356 Views

Last post by mamorani
Sat Mar 13, 2021 10:13 pm
License for ''Fixed-Point Designer'' is not available or installation is incomplete.

Last post by mamorani « Sat Mar 13, 2021 10:12 pm

by mamorani » Sat Mar 13, 2021 10:12 pm

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416 Views

Last post by mamorani
Sat Mar 13, 2021 10:12 pm
License for ''DSP System Toolbox'' is not available or installation is incomplete.

Last post by mamorani « Sat Mar 13, 2021 10:12 pm

by mamorani » Sat Mar 13, 2021 10:12 pm

0 Replies

365 Views

Last post by mamorani
Sat Mar 13, 2021 10:12 pm
License for ''Simulink'' is not available or installation is incomplete

Last post by mamorani « Sat Mar 13, 2021 10:11 pm

by mamorani » Sat Mar 13, 2021 10:11 pm

0 Replies

391 Views

Last post by mamorani
Sat Mar 13, 2021 10:11 pm
'ResetLength'' value of is ignored for cosimulation model for multi rate filters; default value of 2 clock-cycles is us

Last post by mamorani « Sat Mar 13, 2021 10:11 pm

by mamorani » Sat Mar 13, 2021 10:11 pm

0 Replies

349 Views

Last post by mamorani
Sat Mar 13, 2021 10:11 pm
'TestbenchClockEnableDelay'' value of is ignored for cosimulation model for multi rate filters; default value of 1 clo

Last post by mamorani « Sat Mar 13, 2021 10:10 pm

by mamorani » Sat Mar 13, 2021 10:10 pm

0 Replies

413 Views

Last post by mamorani
Sat Mar 13, 2021 10:10 pm
You must pass at least the filter object as the first argument. Optionally, you may also pass one\nproperty-value pair w

Last post by mamorani « Sat Mar 13, 2021 10:10 pm

by mamorani » Sat Mar 13, 2021 10:10 pm

0 Replies

369 Views

Last post by mamorani
Sat Mar 13, 2021 10:10 pm

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