Signal Processing

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Connect to the board over SSH using the specified IP address

Last post by mamorani « Sun Mar 14, 2021 4:23 pm

by mamorani » Sun Mar 14, 2021 4:23 pm

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408 Views

Last post by mamorani
Sun Mar 14, 2021 4:23 pm
Generate VHDL/Verilog code from the selected subsystem, generate simulation model, cosimulation block and traceability f

Last post by mamorani « Sun Mar 14, 2021 4:22 pm

by mamorani » Sun Mar 14, 2021 4:22 pm

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429 Views

Last post by mamorani
Sun Mar 14, 2021 4:22 pm
Run synthesis through third party synthesis workflow

Last post by mamorani « Sun Mar 14, 2021 4:22 pm

by mamorani » Sun Mar 14, 2021 4:22 pm

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441 Views

Last post by mamorani
Sun Mar 14, 2021 4:22 pm
Choose default or custom build Tcl file

Last post by mamorani « Sun Mar 14, 2021 4:22 pm

by mamorani » Sun Mar 14, 2021 4:22 pm

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394 Views

Last post by mamorani
Sun Mar 14, 2021 4:22 pm
Integrate HDL IP Core with Embedded Processor on FPGA

Last post by mamorani « Sun Mar 14, 2021 4:21 pm

by mamorani » Sun Mar 14, 2021 4:21 pm

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405 Views

Last post by mamorani
Sun Mar 14, 2021 4:21 pm
Browse for the Custom Tcl File to be used during the build task

Last post by mamorani « Sun Mar 14, 2021 4:21 pm

by mamorani » Sun Mar 14, 2021 4:21 pm

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447 Views

Last post by mamorani
Sun Mar 14, 2021 4:21 pm
When you complete the tasks, you have a synthesis result report from one of the supported synthesis tools. If the result

Last post by mamorani « Sun Mar 14, 2021 4:21 pm

by mamorani » Sun Mar 14, 2021 4:21 pm

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479 Views

Last post by mamorani
Sun Mar 14, 2021 4:21 pm
HDL Workflow Advisor facilitates RTL code (VHDL/Verilog) and testbench generation from a subsystem, performs synthesis t

Last post by mamorani « Sun Mar 14, 2021 4:20 pm

by mamorani » Sun Mar 14, 2021 4:20 pm

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416 Views

Last post by mamorani
Sun Mar 14, 2021 4:20 pm
Allows AXI4 slave input readback and output pipelining register insertion for the number of ports

Last post by mamorani « Sun Mar 14, 2021 4:20 pm

by mamorani » Sun Mar 14, 2021 4:20 pm

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492 Views

Last post by mamorani
Sun Mar 14, 2021 4:20 pm
Reset Highlighting critical path in Simulink model

Last post by mamorani « Sun Mar 14, 2021 4:19 pm

by mamorani » Sun Mar 14, 2021 4:19 pm

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374 Views

Last post by mamorani
Sun Mar 14, 2021 4:19 pm
Configure model for recommended simulation settings

Last post by mamorani « Sun Mar 14, 2021 4:19 pm

by mamorani » Sun Mar 14, 2021 4:19 pm

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424 Views

Last post by mamorani
Sun Mar 14, 2021 4:19 pm
Integrated Model Advisor environment for HDL code generation and synthesis

Last post by mamorani « Sun Mar 14, 2021 4:19 pm

by mamorani » Sun Mar 14, 2021 4:19 pm

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430 Views

Last post by mamorani
Sun Mar 14, 2021 4:19 pm
Parameter cannot be negative, zero, non-numeric, non-finite value. Choose a compatible numeric value instead.

Last post by mamorani « Sun Mar 14, 2021 4:18 pm

by mamorani » Sun Mar 14, 2021 4:18 pm

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454 Views

Last post by mamorani
Sun Mar 14, 2021 4:18 pm
Parameter min cannot be larger than or equal to max.

Last post by mamorani « Sun Mar 14, 2021 4:18 pm

by mamorani » Sun Mar 14, 2021 4:18 pm

0 Replies

410 Views

Last post by mamorani
Sun Mar 14, 2021 4:18 pm
addRegister cannot handle index vectors of unequal length

Last post by mamorani « Sun Mar 14, 2021 4:17 pm

by mamorani » Sun Mar 14, 2021 4:17 pm

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401 Views

Last post by mamorani
Sun Mar 14, 2021 4:17 pm
addDriverReceiverPair cannot handle vectors of unequal length.

Last post by mamorani « Sun Mar 14, 2021 4:16 pm

by mamorani » Sun Mar 14, 2021 4:16 pm

0 Replies

330 Views

Last post by mamorani
Sun Mar 14, 2021 4:16 pm
addDriverReceiverPair cannot handle index vectors of unequal length.

Last post by mamorani « Sun Mar 14, 2021 4:16 pm

by mamorani » Sun Mar 14, 2021 4:16 pm

0 Replies

357 Views

Last post by mamorani
Sun Mar 14, 2021 4:16 pm
addDriverRegisteredReceiver cannot handle vectors

Last post by mamorani « Sun Mar 14, 2021 4:15 pm

by mamorani » Sun Mar 14, 2021 4:15 pm

0 Replies

393 Views

Last post by mamorani
Sun Mar 14, 2021 4:15 pm
cannot handle non-one-to-one hierarchy connectivity

Last post by mamorani « Sun Mar 14, 2021 4:15 pm

by mamorani » Sun Mar 14, 2021 4:15 pm

0 Replies

412 Views

Last post by mamorani
Sun Mar 14, 2021 4:15 pm
Bad required driver or receiver to addDriverReceiverPar

Last post by mamorani « Sun Mar 14, 2021 4:15 pm

by mamorani » Sun Mar 14, 2021 4:15 pm

0 Replies

327 Views

Last post by mamorani
Sun Mar 14, 2021 4:15 pm
Multipath constraint generation not supported with multiple timing controllers

Last post by mamorani « Sun Mar 14, 2021 4:15 pm

by mamorani » Sun Mar 14, 2021 4:15 pm

0 Replies

362 Views

Last post by mamorani
Sun Mar 14, 2021 4:15 pm
While tracing the output of caught an exception:

Last post by mamorani « Sun Mar 14, 2021 4:14 pm

by mamorani » Sun Mar 14, 2021 4:14 pm

0 Replies

319 Views

Last post by mamorani
Sun Mar 14, 2021 4:14 pm
getComponentHDLPath could not get hpath to component

Last post by mamorani « Sun Mar 14, 2021 4:14 pm

by mamorani » Sun Mar 14, 2021 4:14 pm

0 Replies

577 Views

Last post by mamorani
Sun Mar 14, 2021 4:14 pm
Should not reset the path delimiter used by hdlconnectivity.

Last post by mamorani « Sun Mar 14, 2021 4:13 pm

by mamorani » Sun Mar 14, 2021 4:13 pm

0 Replies

359 Views

Last post by mamorani
Sun Mar 14, 2021 4:13 pm
There exist clock enables in the work list that do not match those in the enable Map for hdlconnectivity.

Last post by mamorani « Sun Mar 14, 2021 4:13 pm

by mamorani » Sun Mar 14, 2021 4:13 pm

0 Replies

367 Views

Last post by mamorani
Sun Mar 14, 2021 4:13 pm

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