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Commented through block(s), , must not be connected as an input to DUT for HDL Testbench generation

Last post by mamorani « Wed Mar 10, 2021 7:18 pm

by mamorani » Wed Mar 10, 2021 7:18 pm

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Last post by mamorani
Wed Mar 10, 2021 7:18 pm
The ' block is commented through. HDL code generation is not supported for blocks that are commented through

Last post by mamorani « Wed Mar 10, 2021 7:18 pm

by mamorani » Wed Mar 10, 2021 7:18 pm

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218 Views

Last post by mamorani
Wed Mar 10, 2021 7:18 pm
Bus output must be defined by a BusObject for HDL code generation

Last post by mamorani « Wed Mar 10, 2021 7:18 pm

by mamorani » Wed Mar 10, 2021 7:18 pm

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207 Views

Last post by mamorani
Wed Mar 10, 2021 7:18 pm
Number of elements of BusObject ' in Subsystem should match with the number of elements of BusObject ' in the refere

Last post by mamorani « Wed Mar 10, 2021 7:17 pm

by mamorani » Wed Mar 10, 2021 7:17 pm

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197 Views

Last post by mamorani
Wed Mar 10, 2021 7:17 pm
Generated model failed to compute block layout. The generated model is valid and can be used to generate a validation mo

Last post by mamorani « Wed Mar 10, 2021 7:17 pm

by mamorani » Wed Mar 10, 2021 7:17 pm

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233 Views

Last post by mamorani
Wed Mar 10, 2021 7:17 pm
In order to generate HDL code for a DUT not in the top level of a model, the subsystem must be able to be treated as an

Last post by mamorani « Wed Mar 10, 2021 7:17 pm

by mamorani » Wed Mar 10, 2021 7:17 pm

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228 Views

Last post by mamorani
Wed Mar 10, 2021 7:17 pm
Aggregate signals not supported: sltype : dimensions

Last post by mamorani « Wed Mar 10, 2021 7:16 pm

by mamorani » Wed Mar 10, 2021 7:16 pm

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232 Views

Last post by mamorani
Wed Mar 10, 2021 7:16 pm
Generate HDL code from MATLAB code (hdlcoder)

Last post by mamorani « Wed Mar 10, 2021 7:15 pm

by mamorani » Wed Mar 10, 2021 7:15 pm

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173 Views

Last post by mamorani
Wed Mar 10, 2021 7:15 pm
defHDLComp API needs a PV pair for the input and output argument. For each input or output, a name and signal type is re

Last post by mamorani « Wed Mar 10, 2021 7:14 pm

by mamorani » Wed Mar 10, 2021 7:14 pm

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Last post by mamorani
Wed Mar 10, 2021 7:14 pm
defHDLComp API needs a function handle or hdlbuiltinimpl.HDLDirectCodeGen for the HDL component argument.

Last post by mamorani « Wed Mar 10, 2021 7:14 pm

by mamorani » Wed Mar 10, 2021 7:14 pm

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Last post by mamorani
Wed Mar 10, 2021 7:14 pm
defHDLComp API needs a character vector for the HDL component name argument

Last post by mamorani « Wed Mar 10, 2021 7:13 pm

by mamorani » Wed Mar 10, 2021 7:13 pm

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185 Views

Last post by mamorani
Wed Mar 10, 2021 7:13 pm
HDL Component Name is a required value for defHDLComp API

Last post by mamorani « Wed Mar 10, 2021 7:13 pm

by mamorani » Wed Mar 10, 2021 7:13 pm

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200 Views

Last post by mamorani
Wed Mar 10, 2021 7:13 pm
Model references are present in the model. Ensure that the referenced models are loaded or are on the search path.

Last post by mamorani « Wed Mar 10, 2021 7:11 pm

by mamorani » Wed Mar 10, 2021 7:11 pm

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Last post by mamorani
Wed Mar 10, 2021 7:11 pm
License for ''HDL Verifier(TM)'' is not available or installation is incomplete.

Last post by mamorani « Wed Mar 10, 2021 7:11 pm

by mamorani » Wed Mar 10, 2021 7:11 pm

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278 Views

Last post by mamorani
Wed Mar 10, 2021 7:11 pm
Cosimulation model generation is not supported for tunable parameters

Last post by mamorani « Wed Mar 10, 2021 7:10 pm

by mamorani » Wed Mar 10, 2021 7:10 pm

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189 Views

Last post by mamorani
Wed Mar 10, 2021 7:10 pm
invalid sample time ( ) found on the cosimulation interface: at port

Last post by mamorani « Wed Mar 10, 2021 7:10 pm

by mamorani » Wed Mar 10, 2021 7:10 pm

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190 Views

Last post by mamorani
Wed Mar 10, 2021 7:10 pm
Cosimulation model generation is not supported in Verilog in the presence of single/double types

Last post by mamorani « Wed Mar 10, 2021 7:09 pm

by mamorani » Wed Mar 10, 2021 7:09 pm

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189 Views

Last post by mamorani
Wed Mar 10, 2021 7:09 pm
Failed to find source for port { ,number,integer} on '\nPlease create a fully connected subsystem when generating the c

Last post by mamorani « Wed Mar 10, 2021 7:07 pm

by mamorani » Wed Mar 10, 2021 7:07 pm

0 Replies

178 Views

Last post by mamorani
Wed Mar 10, 2021 7:07 pm
Generate clock module for FPGA family is not supported

Last post by mamorani « Wed Mar 10, 2021 7:06 pm

by mamorani » Wed Mar 10, 2021 7:06 pm

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176 Views

Last post by mamorani
Wed Mar 10, 2021 7:06 pm
On board, when interface is used, the system clock frequency must be less or equal than 75MHz.

Last post by mamorani « Wed Mar 10, 2021 7:06 pm

by mamorani » Wed Mar 10, 2021 7:06 pm

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170 Views

Last post by mamorani
Wed Mar 10, 2021 7:06 pm
Change FPGA system clock frequency is not supported for

Last post by mamorani « Wed Mar 10, 2021 7:05 pm

by mamorani » Wed Mar 10, 2021 7:05 pm

0 Replies

221 Views

Last post by mamorani
Wed Mar 10, 2021 7:05 pm
UThe system clock frequency on must be between 5MHz to 400MHz

Last post by mamorani « Wed Mar 10, 2021 7:05 pm

by mamorani » Wed Mar 10, 2021 7:05 pm

0 Replies

216 Views

Last post by mamorani
Wed Mar 10, 2021 7:05 pm
Unable to open the synthesis report file for writing

Last post by mamorani « Wed Mar 10, 2021 7:04 pm

by mamorani » Wed Mar 10, 2021 7:04 pm

0 Replies

150 Views

Last post by mamorani
Wed Mar 10, 2021 7:04 pm
Unable to match the starting point because it has been elaborated in Altera or it is inside a Stateflow or a MATLAB Func

Last post by mamorani « Wed Mar 10, 2021 7:03 pm

by mamorani » Wed Mar 10, 2021 7:03 pm

0 Replies

210 Views

Last post by mamorani
Wed Mar 10, 2021 7:03 pm
Nothing to be done. Consider setting showall to on

Last post by mamorani « Wed Mar 10, 2021 7:03 pm

by mamorani » Wed Mar 10, 2021 7:03 pm

0 Replies

169 Views

Last post by mamorani
Wed Mar 10, 2021 7:03 pm

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