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Error occurred during optimization report generation. Attempting to continue code generation

Last post by mamorani « Wed Mar 10, 2021 7:30 pm

by mamorani » Wed Mar 10, 2021 7:30 pm

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176 Views

Last post by mamorani
Wed Mar 10, 2021 7:30 pm
Code generation requested from a non-top level Subsystem. Converting the Subsystem to a model reference failed with the

Last post by mamorani « Wed Mar 10, 2021 7:30 pm

by mamorani » Wed Mar 10, 2021 7:30 pm

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212 Views

Last post by mamorani
Wed Mar 10, 2021 7:30 pm
Port has an Inf rate. Ports of a non-top DUT must have a non-Inf rate in order to be able to generate a runnable valid

Last post by mamorani « Wed Mar 10, 2021 7:30 pm

by mamorani » Wed Mar 10, 2021 7:30 pm

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182 Views

Last post by mamorani
Wed Mar 10, 2021 7:30 pm
Nondefault values of VHDL library name ' are not supported when running the IP Core Generation workflow with Intel Quar

Last post by mamorani « Wed Mar 10, 2021 7:29 pm

by mamorani » Wed Mar 10, 2021 7:29 pm

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181 Views

Last post by mamorani
Wed Mar 10, 2021 7:29 pm
Specify the HTML filename you want to create.

Last post by mamorani « Wed Mar 10, 2021 7:29 pm

by mamorani » Wed Mar 10, 2021 7:29 pm

0 Replies

194 Views

Last post by mamorani
Wed Mar 10, 2021 7:29 pm
Simulink simulation of model ' recorded no data at the DUT input/output ports. Testbench generation cannot continue.

Last post by mamorani « Wed Mar 10, 2021 7:29 pm

by mamorani » Wed Mar 10, 2021 7:29 pm

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188 Views

Last post by mamorani
Wed Mar 10, 2021 7:29 pm
Downstream integration driver needs to be initialized before generating FPGA top level wrapper

Last post by mamorani « Wed Mar 10, 2021 7:28 pm

by mamorani » Wed Mar 10, 2021 7:28 pm

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182 Views

Last post by mamorani
Wed Mar 10, 2021 7:28 pm
Cannot find required information -- please run checkhdl or makehdl first.

Last post by mamorani « Wed Mar 10, 2021 7:28 pm

by mamorani » Wed Mar 10, 2021 7:28 pm

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164 Views

Last post by mamorani
Wed Mar 10, 2021 7:28 pm
When you specify HDL optimizations that can result in overclocking, such as streaming, resource sharing, or clock-rate p

Last post by mamorani « Wed Mar 10, 2021 7:27 pm

by mamorani » Wed Mar 10, 2021 7:27 pm

0 Replies

217 Views

Last post by mamorani
Wed Mar 10, 2021 7:27 pm
Minimize algebraic loop occurrences" not supported on atomic subsystem for HDL code generation.

Last post by mamorani « Wed Mar 10, 2021 7:26 pm

by mamorani » Wed Mar 10, 2021 7:26 pm

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277 Views

Last post by mamorani
Wed Mar 10, 2021 7:26 pm
Mask information for in the original model is not copied to the Subsystem in the generated model and validation model

Last post by mamorani « Wed Mar 10, 2021 7:26 pm

by mamorani » Wed Mar 10, 2021 7:26 pm

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199 Views

Last post by mamorani
Wed Mar 10, 2021 7:26 pm
Errors occurred during model generation of Attempting to continue code generation.e.

Last post by mamorani « Wed Mar 10, 2021 7:25 pm

by mamorani » Wed Mar 10, 2021 7:25 pm

0 Replies

186 Views

Last post by mamorani
Wed Mar 10, 2021 7:25 pm
DUT port ' is a matrix type. Matrix types are not supported at the DUT interface. Consider using a ''Reshape'' block to

Last post by mamorani « Wed Mar 10, 2021 7:25 pm

by mamorani » Wed Mar 10, 2021 7:25 pm

0 Replies

454 Views

Last post by mamorani
Wed Mar 10, 2021 7:25 pm
Matrices are not supported at top level DUT

Last post by mamorani « Wed Mar 10, 2021 7:25 pm

by mamorani » Wed Mar 10, 2021 7:25 pm

0 Replies

189 Views

Last post by mamorani
Wed Mar 10, 2021 7:25 pm
String type is not supported for HDL Code Generation.

Last post by mamorani « Wed Mar 10, 2021 7:24 pm

by mamorani » Wed Mar 10, 2021 7:24 pm

0 Replies

182 Views

Last post by mamorani
Wed Mar 10, 2021 7:24 pm
Integer delay initial conditions do not match delay length

Last post by mamorani « Wed Mar 10, 2021 7:24 pm

by mamorani » Wed Mar 10, 2021 7:24 pm

0 Replies

198 Views

Last post by mamorani
Wed Mar 10, 2021 7:24 pm
Internal error: duplicate default configuration statements detected in

Last post by mamorani « Wed Mar 10, 2021 7:24 pm

by mamorani » Wed Mar 10, 2021 7:24 pm

0 Replies

193 Views

Last post by mamorani
Wed Mar 10, 2021 7:24 pm
Subsystem contains an Ifaction port, which is unsupported

Last post by mamorani « Wed Mar 10, 2021 7:23 pm

by mamorani » Wed Mar 10, 2021 7:23 pm

0 Replies

219 Views

Last post by mamorani
Wed Mar 10, 2021 7:23 pm
User specified option for ignore data checking: is less than maximum latency of the DUT: . This may cause HDL simulat

Last post by mamorani « Wed Mar 10, 2021 7:23 pm

by mamorani » Wed Mar 10, 2021 7:23 pm

0 Replies

208 Views

Last post by mamorani
Wed Mar 10, 2021 7:23 pm
Iternal Error: HDL checksum file for model does not exist.

Last post by mamorani « Wed Mar 10, 2021 7:23 pm

by mamorani » Wed Mar 10, 2021 7:23 pm

0 Replies

358 Views

Last post by mamorani
Wed Mar 10, 2021 7:23 pm
A Goto/From connection crosses the HDL DUT boundary. This is not supported.

Last post by mamorani « Wed Mar 10, 2021 7:22 pm

by mamorani » Wed Mar 10, 2021 7:22 pm

0 Replies

194 Views

Last post by mamorani
Wed Mar 10, 2021 7:22 pm
Rapid Accelerator mode not supported while generating HDL testbench vectors. The model generated will use Accelerator mo

Last post by mamorani « Wed Mar 10, 2021 7:22 pm

by mamorani » Wed Mar 10, 2021 7:22 pm

0 Replies

178 Views

Last post by mamorani
Wed Mar 10, 2021 7:22 pm
Function call port types are not supported

Last post by mamorani « Wed Mar 10, 2021 7:22 pm

by mamorani » Wed Mar 10, 2021 7:22 pm

0 Replies

190 Views

Last post by mamorani
Wed Mar 10, 2021 7:22 pm
Internal Error: Simulink timeseries data is missing for DUT port Testbench generation cannot continue

Last post by mamorani « Wed Mar 10, 2021 7:20 pm

by mamorani » Wed Mar 10, 2021 7:20 pm

0 Replies

179 Views

Last post by mamorani
Wed Mar 10, 2021 7:20 pm
The '' subsystem is commented through. HDL code generation is not supported for subsystems that are commented through

Last post by mamorani « Wed Mar 10, 2021 7:19 pm

by mamorani » Wed Mar 10, 2021 7:19 pm

0 Replies

246 Views

Last post by mamorani
Wed Mar 10, 2021 7:19 pm

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