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Delay block has a nonvirtual bus type on its input signal, and is in a network hierarchy where optimizations have been

Last post by mamorani « Wed Mar 10, 2021 10:06 pm

by mamorani » Wed Mar 10, 2021 10:06 pm

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Last post by mamorani
Wed Mar 10, 2021 10:06 pm
Bit width of block ' exceeds 127 bits; this may abort code generation during ''makehdl''

Last post by mamorani « Wed Mar 10, 2021 10:06 pm

by mamorani » Wed Mar 10, 2021 10:06 pm

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Last post by mamorani
Wed Mar 10, 2021 10:06 pm
The following table describes blocks for which errors, warnings or messages were reported.

Last post by mamorani « Wed Mar 10, 2021 10:05 pm

by mamorani » Wed Mar 10, 2021 10:05 pm

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Last post by mamorani
Wed Mar 10, 2021 10:05 pm
Chain of if...else if constructs must not exceed levels, in MATLAB function block "

Last post by mamorani « Wed Mar 10, 2021 10:04 pm

by mamorani » Wed Mar 10, 2021 10:04 pm

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Last post by mamorani
Wed Mar 10, 2021 10:04 pm
Nesting in if-else constructs should not be deeper than the levels, in MATLAB Function block

Last post by mamorani « Wed Mar 10, 2021 10:03 pm

by mamorani » Wed Mar 10, 2021 10:03 pm

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194 Views

Last post by mamorani
Wed Mar 10, 2021 10:03 pm
Do not describe more than statements (if/case/while/for/ loop) separately within a single process block, found in MATL

Last post by mamorani « Wed Mar 10, 2021 10:03 pm

by mamorani » Wed Mar 10, 2021 10:03 pm

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217 Views

Last post by mamorani
Wed Mar 10, 2021 10:03 pm
Reset signals found on network . Cannot remove reset signal

Last post by mamorani « Wed Mar 10, 2021 10:02 pm

by mamorani » Wed Mar 10, 2021 10:02 pm

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207 Views

Last post by mamorani
Wed Mar 10, 2021 10:02 pm
Clock enable signals found on network . Cannot remove clock enable signal.

Last post by mamorani « Wed Mar 10, 2021 10:02 pm

by mamorani » Wed Mar 10, 2021 10:02 pm

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197 Views

Last post by mamorani
Wed Mar 10, 2021 10:02 pm
Vector types present in the model; LSB of vectors will not be zero in the generated code.

Last post by mamorani « Wed Mar 10, 2021 10:02 pm

by mamorani » Wed Mar 10, 2021 10:02 pm

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190 Views

Last post by mamorani
Wed Mar 10, 2021 10:02 pm
Enabling Industry mode will overwrite certain codegeneration options

Last post by mamorani « Wed Mar 10, 2021 10:01 pm

by mamorani » Wed Mar 10, 2021 10:01 pm

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202 Views

Last post by mamorani
Wed Mar 10, 2021 10:01 pm
Found vector port Vector port is not currently supported. Set the HDL code generation option "Scalarize ports" as "on"

Last post by mamorani « Wed Mar 10, 2021 9:57 pm

by mamorani » Wed Mar 10, 2021 9:57 pm

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216 Views

Last post by mamorani
Wed Mar 10, 2021 9:57 pm
No board was selected. Select a board from the "Board Name" list

Last post by mamorani « Wed Mar 10, 2021 9:57 pm

by mamorani » Wed Mar 10, 2021 9:57 pm

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207 Views

Last post by mamorani
Wed Mar 10, 2021 9:57 pm
No board was selected. Select a board from the "Board Name" list

Last post by mamorani « Wed Mar 10, 2021 9:57 pm

by mamorani » Wed Mar 10, 2021 9:57 pm

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203 Views

Last post by mamorani
Wed Mar 10, 2021 9:57 pm
A noncustom simulation tool is needed for HDL code coverage to be enabled, the option will be ignored.

Last post by mamorani « Wed Mar 10, 2021 9:56 pm

by mamorani » Wed Mar 10, 2021 9:56 pm

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204 Views

Last post by mamorani
Wed Mar 10, 2021 9:56 pm
HDL Verifier is not available requires HDL Verifier installation and license.

Last post by mamorani « Wed Mar 10, 2021 9:56 pm

by mamorani » Wed Mar 10, 2021 9:56 pm

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223 Views

Last post by mamorani
Wed Mar 10, 2021 9:56 pm
Choose customization options for FPGA-in-the-Loop. One can add additional files to table below for HDL Coder black-box s

Last post by mamorani « Wed Mar 10, 2021 9:55 pm

by mamorani » Wed Mar 10, 2021 9:55 pm

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211 Views

Last post by mamorani
Wed Mar 10, 2021 9:55 pm
Specify additional source files for the HDL design

Last post by mamorani « Wed Mar 10, 2021 9:54 pm

by mamorani » Wed Mar 10, 2021 9:54 pm

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Last post by mamorani
Wed Mar 10, 2021 9:54 pm
FPGA-in-the-Loop Test Bench Generation

Last post by mamorani « Wed Mar 10, 2021 9:53 pm

by mamorani » Wed Mar 10, 2021 9:53 pm

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237 Views

Last post by mamorani
Wed Mar 10, 2021 9:53 pm
Found unsupported double data type for port . Convert the design to fixed-point to solve this problem

Last post by mamorani « Wed Mar 10, 2021 9:52 pm

by mamorani » Wed Mar 10, 2021 9:52 pm

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240 Views

Last post by mamorani
Wed Mar 10, 2021 9:52 pm
Skipping simulation of test bench since MATLAB test bench is not available

Last post by mamorani « Wed Mar 10, 2021 9:51 pm

by mamorani » Wed Mar 10, 2021 9:51 pm

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268 Views

Last post by mamorani
Wed Mar 10, 2021 9:51 pm
To manually run the generated test bench, execute the following commands in MATLAB:

Last post by mamorani « Wed Mar 10, 2021 9:50 pm

by mamorani » Wed Mar 10, 2021 9:50 pm

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239 Views

Last post by mamorani
Wed Mar 10, 2021 9:50 pm
Checking compatibility with test bench generation

Last post by mamorani « Wed Mar 10, 2021 9:48 pm

by mamorani » Wed Mar 10, 2021 9:48 pm

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243 Views

Last post by mamorani
Wed Mar 10, 2021 9:48 pm
Rate mismatch at the output of Rate Transition block connected to port Change the output sample time of ' to match the

Last post by mamorani « Wed Mar 10, 2021 9:45 pm

by mamorani » Wed Mar 10, 2021 9:45 pm

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257 Views

Last post by mamorani
Wed Mar 10, 2021 9:45 pm
Internal Error: ''Status'' field in the return structure of validate function of class should be of data type double.

Last post by mamorani « Wed Mar 10, 2021 9:44 pm

by mamorani » Wed Mar 10, 2021 9:44 pm

0 Replies

277 Views

Last post by mamorani
Wed Mar 10, 2021 9:44 pm
Internal Error: Invalid Return argument from validate function of class not expecting a multi dimensional structure

Last post by mamorani « Wed Mar 10, 2021 9:44 pm

by mamorani » Wed Mar 10, 2021 9:44 pm

0 Replies

240 Views

Last post by mamorani
Wed Mar 10, 2021 9:44 pm

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