Signal Processing

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Delay balancing failed due to an artificial feedback loop. Consider disabling the 'Generate instantiable code for functi

Last post by mamorani « Wed Mar 10, 2021 11:07 pm

by mamorani » Wed Mar 10, 2021 11:07 pm

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Last post by mamorani
Wed Mar 10, 2021 11:07 pm
HDL Conformance check complete with errors warnings, and messages

Last post by mamorani « Wed Mar 10, 2021 11:06 pm

by mamorani » Wed Mar 10, 2021 11:06 pm

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212 Views

Last post by mamorani
Wed Mar 10, 2021 11:06 pm
To automatically open the conformance check report, , select 'Check HDL conformance' report on GUI, or set CheckConforma

Last post by mamorani « Wed Mar 10, 2021 11:06 pm

by mamorani » Wed Mar 10, 2021 11:06 pm

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230 Views

Last post by mamorani
Wed Mar 10, 2021 11:06 pm
Xilinx system generator subsystem entity causes name conflict. This must be renamed.

Last post by mamorani « Wed Mar 10, 2021 11:05 pm

by mamorani » Wed Mar 10, 2021 11:05 pm

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277 Views

Last post by mamorani
Wed Mar 10, 2021 11:05 pm
Signal with unsupported word length of is detected at the input of block . HDL code generation for block with fixed-p

Last post by mamorani « Wed Mar 10, 2021 11:02 pm

by mamorani » Wed Mar 10, 2021 11:02 pm

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234 Views

Last post by mamorani
Wed Mar 10, 2021 11:02 pm
Word length must be a positive integer

Last post by mamorani « Wed Mar 10, 2021 11:02 pm

by mamorani » Wed Mar 10, 2021 11:02 pm

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207 Views

Last post by mamorani
Wed Mar 10, 2021 11:02 pm
Signal with unsupported word length of is detected

Last post by mamorani « Wed Mar 10, 2021 11:01 pm

by mamorani » Wed Mar 10, 2021 11:01 pm

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235 Views

Last post by mamorani
Wed Mar 10, 2021 11:01 pm
Setting Simulink word length to maximum value of 128; HDL results may not match

Last post by mamorani « Wed Mar 10, 2021 11:01 pm

by mamorani » Wed Mar 10, 2021 11:01 pm

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261 Views

Last post by mamorani
Wed Mar 10, 2021 11:01 pm
Generating HDL code for a variant subsystem in the model not supported

Last post by mamorani « Wed Mar 10, 2021 11:00 pm

by mamorani » Wed Mar 10, 2021 11:00 pm

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212 Views

Last post by mamorani
Wed Mar 10, 2021 11:00 pm
Signal with unsupported word length of is detected at the input of block HDL code generation for block with fixed-poin

Last post by mamorani « Wed Mar 10, 2021 11:00 pm

by mamorani » Wed Mar 10, 2021 11:00 pm

0 Replies

245 Views

Last post by mamorani
Wed Mar 10, 2021 11:00 pm
Slope and Bias data-types not supported for HDL Code generation

Last post by mamorani « Wed Mar 10, 2021 10:59 pm

by mamorani » Wed Mar 10, 2021 10:59 pm

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217 Views

Last post by mamorani
Wed Mar 10, 2021 10:59 pm
Unconnected bidirectional port in component of network found

Last post by mamorani « Wed Mar 10, 2021 10:59 pm

by mamorani » Wed Mar 10, 2021 10:59 pm

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233 Views

Last post by mamorani
Wed Mar 10, 2021 10:59 pm
Too many matches for subsystem ' in the model - please provide a more specific DUT name

Last post by mamorani « Wed Mar 10, 2021 10:58 pm

by mamorani » Wed Mar 10, 2021 10:58 pm

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209 Views

Last post by mamorani
Wed Mar 10, 2021 10:58 pm
Word length must be 2 or more for a signed data type

Last post by mamorani « Wed Mar 10, 2021 10:58 pm

by mamorani » Wed Mar 10, 2021 10:58 pm

0 Replies

210 Views

Last post by mamorani
Wed Mar 10, 2021 10:58 pm
The output sample rate must be an integer ratio of the input sample rate

Last post by mamorani « Wed Mar 10, 2021 10:57 pm

by mamorani » Wed Mar 10, 2021 10:57 pm

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190 Views

Last post by mamorani
Wed Mar 10, 2021 10:57 pm
The combination of coder options chosen require an overclocking factor of which violates the MaxOversampling

Last post by mamorani « Wed Mar 10, 2021 10:57 pm

by mamorani » Wed Mar 10, 2021 10:57 pm

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163 Views

Last post by mamorani
Wed Mar 10, 2021 10:57 pm
There are no models open; could not find subsystem

Last post by mamorani « Wed Mar 10, 2021 10:57 pm

by mamorani » Wed Mar 10, 2021 10:57 pm

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308 Views

Last post by mamorani
Wed Mar 10, 2021 10:57 pm
Invalid number of arguments, no object specified

Last post by mamorani « Wed Mar 10, 2021 10:56 pm

by mamorani » Wed Mar 10, 2021 10:56 pm

0 Replies

196 Views

Last post by mamorani
Wed Mar 10, 2021 10:56 pm
Could not find ''generateHDLFor'' in the control file\nApplying control file on the whole model\

Last post by mamorani « Wed Mar 10, 2021 10:55 pm

by mamorani » Wed Mar 10, 2021 10:55 pm

0 Replies

187 Views

Last post by mamorani
Wed Mar 10, 2021 10:55 pm
Unable to check out a license for the DSP System Toolbox

Last post by mamorani « Wed Mar 10, 2021 10:54 pm

by mamorani » Wed Mar 10, 2021 10:54 pm

0 Replies

214 Views

Last post by mamorani
Wed Mar 10, 2021 10:54 pm
There is no default model; please load a model

Last post by mamorani « Wed Mar 10, 2021 10:54 pm

by mamorani » Wed Mar 10, 2021 10:54 pm

0 Replies

197 Views

Last post by mamorani
Wed Mar 10, 2021 10:54 pm
Please specify FFT block name when calling hdlblkmask_fft(''initial_delay'', ''BlockName''

Last post by mamorani « Wed Mar 10, 2021 10:53 pm

by mamorani » Wed Mar 10, 2021 10:53 pm

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211 Views

Last post by mamorani
Wed Mar 10, 2021 10:53 pm
and are identical atomic subsystems that are located in different conditional subsystems. Code sharing between these su

Last post by mamorani « Wed Mar 10, 2021 10:53 pm

by mamorani » Wed Mar 10, 2021 10:53 pm

0 Replies

313 Views

Last post by mamorani
Wed Mar 10, 2021 10:53 pm
and are identical model references that are located in different conditional subsystems. Code sharing between these mo

Last post by mamorani « Wed Mar 10, 2021 10:52 pm

by mamorani » Wed Mar 10, 2021 10:52 pm

0 Replies

222 Views

Last post by mamorani
Wed Mar 10, 2021 10:52 pm
The model has the Rebuild parameter on the Model Referencing pane of the Configuration Parameters dialog box set to Neve

Last post by mamorani « Wed Mar 10, 2021 10:51 pm

by mamorani » Wed Mar 10, 2021 10:51 pm

0 Replies

215 Views

Last post by mamorani
Wed Mar 10, 2021 10:51 pm

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