Signal Processing

New Topic

3049 topics

Page 84 of 122
- Jump to page:
Previous
1
…
82
83
84
85
86
…
122
Next

Topics

Replies

Views

Last post

step method for child System objects can only be called from stepImpl method of parent System object for HDL code genera

Last post by mamorani « Thu Mar 11, 2021 3:13 pm

by mamorani » Thu Mar 11, 2021 3:13 pm

0 Replies

237 Views

Last post by mamorani
Thu Mar 11, 2021 3:13 pm
Tunable parameter used in '' , has rate ' . The rate differs from other usages in the same design, which have rate . Tun

Last post by mamorani « Thu Mar 11, 2021 3:11 pm

by mamorani » Thu Mar 11, 2021 3:11 pm

0 Replies

226 Views

Last post by mamorani
Thu Mar 11, 2021 3:11 pm
A tunable parameter and input port have the same name, . Fix this error by renaming the tunable parameter or the input

Last post by mamorani « Thu Mar 11, 2021 3:09 pm

by mamorani » Thu Mar 11, 2021 3:09 pm

0 Replies

244 Views

Last post by mamorani
Thu Mar 11, 2021 3:09 pm
Tunable parameter is used in Trigger as clock mode. This is not supported for HDL code generation.

Last post by mamorani « Thu Mar 11, 2021 3:09 pm

by mamorani » Thu Mar 11, 2021 3:09 pm

0 Replies

271 Views

Last post by mamorani
Thu Mar 11, 2021 3:09 pm
A tunable parameter and input port, which may have originated from a From block, have the same name To fix this error,

Last post by mamorani « Thu Mar 11, 2021 3:08 pm

by mamorani » Thu Mar 11, 2021 3:08 pm

0 Replies

235 Views

Last post by mamorani
Thu Mar 11, 2021 3:08 pm
System objects inside Stateflow chart are not supported for HDL Code generation.

Last post by mamorani « Thu Mar 11, 2021 3:08 pm

by mamorani » Thu Mar 11, 2021 3:08 pm

0 Replies

304 Views

Last post by mamorani
Thu Mar 11, 2021 3:08 pm
System blocks and MATLAB function blocks, containing System objects, are not supported for HDL code generation when the

Last post by mamorani « Thu Mar 11, 2021 3:07 pm

by mamorani » Thu Mar 11, 2021 3:07 pm

0 Replies

239 Views

Last post by mamorani
Thu Mar 11, 2021 3:07 pm
Array of System objects and System objects in struct fields are not supported for HDL code generation.

Last post by mamorani « Thu Mar 11, 2021 3:07 pm

by mamorani » Thu Mar 11, 2021 3:07 pm

0 Replies

222 Views

Last post by mamorani
Thu Mar 11, 2021 3:07 pm
For HDL code generation, assign function inputs or constant values to public tunable properties of System objects.

Last post by mamorani « Thu Mar 11, 2021 3:07 pm

by mamorani » Thu Mar 11, 2021 3:07 pm

0 Replies

287 Views

Last post by mamorani
Thu Mar 11, 2021 3:07 pm
Public tunable property assignment from outside the System object is not supported for HDL code generation.

Last post by mamorani « Thu Mar 11, 2021 3:06 pm

by mamorani » Thu Mar 11, 2021 3:06 pm

0 Replies

211 Views

Last post by mamorani
Thu Mar 11, 2021 3:06 pm
System objects with tunable or DiscreteState properties must be assigned to persistent variables for HDL code generation

Last post by mamorani « Thu Mar 11, 2021 3:06 pm

by mamorani » Thu Mar 11, 2021 3:06 pm

0 Replies

265 Views

Last post by mamorani
Thu Mar 11, 2021 3:06 pm
Multiple System objects cannot be assigned to the same variable for HDL code generation.

Last post by mamorani « Thu Mar 11, 2021 3:06 pm

by mamorani » Thu Mar 11, 2021 3:06 pm

0 Replies

227 Views

Last post by mamorani
Thu Mar 11, 2021 3:06 pm
System object cannot be used inside other System objects for HDL code generation.

Last post by mamorani « Thu Mar 11, 2021 3:05 pm

by mamorani » Thu Mar 11, 2021 3:05 pm

0 Replies

216 Views

Last post by mamorani
Thu Mar 11, 2021 3:05 pm
HDL code generation does not support calling custom public methods or setting public tunable properties of System object

Last post by mamorani « Thu Mar 11, 2021 3:05 pm

by mamorani » Thu Mar 11, 2021 3:05 pm

0 Replies

218 Views

Last post by mamorani
Thu Mar 11, 2021 3:05 pm
A property used in file line number, integer}, col , number, integer}, is also used outside this function. HDL code g

Last post by mamorani « Thu Mar 11, 2021 3:04 pm

by mamorani » Thu Mar 11, 2021 3:04 pm

0 Replies

265 Views

Last post by mamorani
Thu Mar 11, 2021 3:04 pm
System blocks and MATLAB function blocks, containing system objects, are not supported for HDL code generation when the

Last post by mamorani « Thu Mar 11, 2021 3:04 pm

by mamorani » Thu Mar 11, 2021 3:04 pm

0 Replies

246 Views

Last post by mamorani
Thu Mar 11, 2021 3:04 pm
Internal Error: failed to run system object lowering for hdl:

Last post by mamorani « Thu Mar 11, 2021 3:03 pm

by mamorani » Thu Mar 11, 2021 3:03 pm

0 Replies

422 Views

Last post by mamorani
Thu Mar 11, 2021 3:03 pm
Internal Error: failed to set latency for System objects:

Last post by mamorani « Thu Mar 11, 2021 3:03 pm

by mamorani » Thu Mar 11, 2021 3:03 pm

0 Replies

223 Views

Last post by mamorani
Thu Mar 11, 2021 3:03 pm
Error: Two signals with same name do not have the same type:

Last post by mamorani « Thu Mar 11, 2021 3:02 pm

by mamorani » Thu Mar 11, 2021 3:02 pm

0 Replies

236 Views

Last post by mamorani
Thu Mar 11, 2021 3:02 pm
Protected model with a support for HDL Code generation cannot be created if a model uses tunable parameters within it

Last post by mamorani « Thu Mar 11, 2021 3:02 pm

by mamorani » Thu Mar 11, 2021 3:02 pm

0 Replies

251 Views

Last post by mamorani
Thu Mar 11, 2021 3:02 pm
'BaseType'' requires a numeric type handle as a value, not

Last post by mamorani « Thu Mar 11, 2021 3:01 pm

by mamorani » Thu Mar 11, 2021 3:01 pm

0 Replies

234 Views

Last post by mamorani
Thu Mar 11, 2021 3:01 pm
The slice method requires either ''bounds'' or ''index'' to be specified

Last post by mamorani « Thu Mar 11, 2021 3:01 pm

by mamorani » Thu Mar 11, 2021 3:01 pm

0 Replies

219 Views

Last post by mamorani
Thu Mar 11, 2021 3:01 pm
Error: lowering pir native comps to MATLAB code failed with the error message:

Last post by mamorani « Thu Mar 11, 2021 3:00 pm

by mamorani » Thu Mar 11, 2021 3:00 pm

0 Replies

245 Views

Last post by mamorani
Thu Mar 11, 2021 3:00 pm
Language parameter is not valid. Accepted values are VHDL, Verilog, SystemVerilog, Verilog2001, DOT, CKT, Target, EDIF,

Last post by mamorani « Thu Mar 11, 2021 3:00 pm

by mamorani » Thu Mar 11, 2021 3:00 pm

0 Replies

209 Views

Last post by mamorani
Thu Mar 11, 2021 3:00 pm
Error: Invalid port name: nvalid syntax: ''nRefNum.inPortName'' (or) ''nRefNum.cRefNum.outPortName'

Last post by mamorani « Thu Mar 11, 2021 2:59 pm

by mamorani » Thu Mar 11, 2021 2:59 pm

0 Replies

245 Views

Last post by mamorani
Thu Mar 11, 2021 2:59 pm

New Topic

3049 topics

Page 84 of 122
- Jump to page:
Previous
1
…
82
83
84
85
86
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 13 guests

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum