Signal Processing

New Topic

3049 topics

Page 81 of 122
- Jump to page:
Previous
1
…
79
80
81
82
83
…
122
Next

Topics

Replies

Views

Last post

Unable to generate hyperlinked comments in the traceability report for code-to-model navigation. ''Traceability'' option

Last post by mamorani « Fri Mar 12, 2021 9:46 am

by mamorani » Fri Mar 12, 2021 9:46 am

0 Replies

171 Views

Last post by mamorani
Fri Mar 12, 2021 9:46 am
Ignoring ''MaxComputationLatency'' parameter as it is no longer supported. Use clock-rate pipelining in conjunction with

Last post by mamorani « Fri Mar 12, 2021 9:45 am

by mamorani » Fri Mar 12, 2021 9:45 am

0 Replies

156 Views

Last post by mamorani
Fri Mar 12, 2021 9:45 am
The enabled resettable delay is not running at the fastest rate in the DUT. This can cause a simulation mismatch if th

Last post by mamorani « Fri Mar 12, 2021 9:45 am

by mamorani » Fri Mar 12, 2021 9:45 am

0 Replies

174 Views

Last post by mamorani
Fri Mar 12, 2021 9:45 am
Characterization spec did not match for block Expected dimension , number, integer}, found number, integer}

Last post by mamorani « Fri Mar 12, 2021 9:44 am

by mamorani » Fri Mar 12, 2021 9:44 am

0 Replies

217 Views

Last post by mamorani
Fri Mar 12, 2021 9:44 am
Timing characterization data not found for block

Last post by mamorani « Fri Mar 12, 2021 9:44 am

by mamorani » Fri Mar 12, 2021 9:44 am

0 Replies

150 Views

Last post by mamorani
Fri Mar 12, 2021 9:44 am
Block not characterized for this configuration

Last post by mamorani « Fri Mar 12, 2021 9:43 am

by mamorani » Fri Mar 12, 2021 9:43 am

0 Replies

156 Views

Last post by mamorani
Fri Mar 12, 2021 9:43 am
case-expr is of typ and case-choice is of type . switch statement requires case-expr and case-choice to be of identica

Last post by mamorani « Fri Mar 12, 2021 9:43 am

by mamorani » Fri Mar 12, 2021 9:43 am

0 Replies

182 Views

Last post by mamorani
Fri Mar 12, 2021 9:43 am
Delay block has a nonvirtual bus type on its input signal, and is in a network hierarchy where optimizations have been

Last post by mamorani « Fri Mar 12, 2021 9:43 am

by mamorani » Fri Mar 12, 2021 9:43 am

0 Replies

170 Views

Last post by mamorani
Fri Mar 12, 2021 9:43 am
Bit width of block exceeds 127 bits; this may abort code generation during ''makehdl''

Last post by mamorani « Fri Mar 12, 2021 9:42 am

by mamorani » Fri Mar 12, 2021 9:42 am

0 Replies

165 Views

Last post by mamorani
Fri Mar 12, 2021 9:42 am
The following table describes blocks for which errors, warnings or messages were reported.

Last post by mamorani « Fri Mar 12, 2021 9:42 am

by mamorani » Fri Mar 12, 2021 9:42 am

0 Replies

195 Views

Last post by mamorani
Fri Mar 12, 2021 9:42 am
Chain of if...else if constructs must not exceed levels, in MATLAB function block

Last post by mamorani « Fri Mar 12, 2021 9:41 am

by mamorani » Fri Mar 12, 2021 9:41 am

0 Replies

177 Views

Last post by mamorani
Fri Mar 12, 2021 9:41 am
Nesting in if-else constructs should not be deeper than the levels, in MATLAB Function block

Last post by mamorani « Fri Mar 12, 2021 9:41 am

by mamorani » Fri Mar 12, 2021 9:41 am

0 Replies

176 Views

Last post by mamorani
Fri Mar 12, 2021 9:41 am
Do not describe more than statements (if/case/while/for/ loop) separately within a single process block, found in MATL

Last post by mamorani « Fri Mar 12, 2021 9:40 am

by mamorani » Fri Mar 12, 2021 9:40 am

0 Replies

145 Views

Last post by mamorani
Fri Mar 12, 2021 9:40 am
Reset signals found on network . Cannot remove reset signal

Last post by mamorani « Fri Mar 12, 2021 9:40 am

by mamorani » Fri Mar 12, 2021 9:40 am

0 Replies

196 Views

Last post by mamorani
Fri Mar 12, 2021 9:40 am
Clock enable signals found on network Cannot remove clock enable signal

Last post by mamorani « Fri Mar 12, 2021 9:39 am

by mamorani » Fri Mar 12, 2021 9:39 am

0 Replies

176 Views

Last post by mamorani
Fri Mar 12, 2021 9:39 am
Vector types present in the model; LSB of vectors will not be zero in the generated code.

Last post by mamorani « Fri Mar 12, 2021 9:39 am

by mamorani » Fri Mar 12, 2021 9:39 am

0 Replies

125 Views

Last post by mamorani
Fri Mar 12, 2021 9:39 am
Enabling Industry mode will overwrite certain codegeneration options.

Last post by mamorani « Fri Mar 12, 2021 9:38 am

by mamorani » Fri Mar 12, 2021 9:38 am

0 Replies

163 Views

Last post by mamorani
Fri Mar 12, 2021 9:38 am
Found vector port . Vector port is not currently supported. Set the HDL code generation option "Scalarize ports" as "on

Last post by mamorani « Fri Mar 12, 2021 9:37 am

by mamorani » Fri Mar 12, 2021 9:37 am

0 Replies

153 Views

Last post by mamorani
Fri Mar 12, 2021 9:37 am
A noncustom simulation tool is needed for HDL code coverage to be enabled, the option will be ignored.

Last post by mamorani « Fri Mar 12, 2021 9:37 am

by mamorani » Fri Mar 12, 2021 9:37 am

0 Replies

148 Views

Last post by mamorani
Fri Mar 12, 2021 9:37 am
HDL Verifier is not available. requires HDL Verifier installation and license.

Last post by mamorani « Fri Mar 12, 2021 9:37 am

by mamorani » Fri Mar 12, 2021 9:37 am

0 Replies

178 Views

Last post by mamorani
Fri Mar 12, 2021 9:37 am
Choose customization options for FPGA-in-the-Loop. One can add additional files to table below for HDL Coder black-box s

Last post by mamorani « Fri Mar 12, 2021 9:36 am

by mamorani » Fri Mar 12, 2021 9:36 am

0 Replies

182 Views

Last post by mamorani
Fri Mar 12, 2021 9:36 am
Specify additional source files for the HDL design

Last post by mamorani « Fri Mar 12, 2021 9:36 am

by mamorani » Fri Mar 12, 2021 9:36 am

0 Replies

141 Views

Last post by mamorani
Fri Mar 12, 2021 9:36 am
FPGA-in-the-Loop Test Bench Generation

Last post by mamorani « Fri Mar 12, 2021 9:36 am

by mamorani » Fri Mar 12, 2021 9:36 am

0 Replies

154 Views

Last post by mamorani
Fri Mar 12, 2021 9:36 am
Found unsupported double data type for port Convert the design to fixed-point to solve this problem.

Last post by mamorani « Fri Mar 12, 2021 9:35 am

by mamorani » Fri Mar 12, 2021 9:35 am

0 Replies

131 Views

Last post by mamorani
Fri Mar 12, 2021 9:35 am
Skipping generation of test bench execution function since MATLAB test bench is not available

Last post by mamorani « Fri Mar 12, 2021 9:35 am

by mamorani » Fri Mar 12, 2021 9:35 am

0 Replies

155 Views

Last post by mamorani
Fri Mar 12, 2021 9:35 am

New Topic

3049 topics

Page 81 of 122
- Jump to page:
Previous
1
…
79
80
81
82
83
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 9 guests

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum