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Different input and output sample times are not supported for this block. Consider either adding a rate transition block

Last post by mamorani « Fri Mar 12, 2021 11:49 am

by mamorani » Fri Mar 12, 2021 11:49 am

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136 Views

Last post by mamorani
Fri Mar 12, 2021 11:49 am
Bus types are not supported on Delay block when it is configured to have a reset port

Last post by mamorani « Fri Mar 12, 2021 11:48 am

by mamorani » Fri Mar 12, 2021 11:48 am

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140 Views

Last post by mamorani
Fri Mar 12, 2021 11:48 am
Delay blocks with bus inputs cannot have non zero Initial condition for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 11:48 am

by mamorani » Fri Mar 12, 2021 11:48 am

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193 Views

Last post by mamorani
Fri Mar 12, 2021 11:48 am
CDATA[ <a href="matlab:configset.internal.open(' ,''BalanceDelays'')">''BalanceDelays''</a> is set to ''Off'' for the mo

Last post by mamorani « Fri Mar 12, 2021 11:47 am

by mamorani » Fri Mar 12, 2021 11:47 am

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181 Views

Last post by mamorani
Fri Mar 12, 2021 11:47 am
The HDL Implementation for the DUT must be specified as 'Module'.

Last post by mamorani « Fri Mar 12, 2021 11:47 am

by mamorani » Fri Mar 12, 2021 11:47 am

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147 Views

Last post by mamorani
Fri Mar 12, 2021 11:47 am
The ''DataTypeOverride'' parameter must be set to ''UseLocalSettings'', ''Off'', or ''ForceOff'' on model ' for HDL cod

Last post by mamorani « Fri Mar 12, 2021 11:47 am

by mamorani » Fri Mar 12, 2021 11:47 am

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225 Views

Last post by mamorani
Fri Mar 12, 2021 11:47 am
In Discrete Transfer Fcn block, ExternalReset was set to this block supports HDL code generation only when ExternalRese

Last post by mamorani « Fri Mar 12, 2021 11:46 am

by mamorani » Fri Mar 12, 2021 11:46 am

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191 Views

Last post by mamorani
Fri Mar 12, 2021 11:46 am
Inherit via internal rule in Discrete Transfer Fcn block is not supported for HDL code generation. To fix this, change t

Last post by mamorani « Fri Mar 12, 2021 11:46 am

by mamorani » Fri Mar 12, 2021 11:46 am

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157 Views

Last post by mamorani
Fri Mar 12, 2021 11:46 am
The input and output sample times of a Data Type Conversion block much match.

Last post by mamorani « Fri Mar 12, 2021 11:46 am

by mamorani » Fri Mar 12, 2021 11:46 am

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149 Views

Last post by mamorani
Fri Mar 12, 2021 11:46 am
DSPStyle setting has no effect. The DSPStyle option is not supported for blocks with floating-point inputs

Last post by mamorani « Fri Mar 12, 2021 11:45 am

by mamorani » Fri Mar 12, 2021 11:45 am

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168 Views

Last post by mamorani
Fri Mar 12, 2021 11:45 am
DSPStyle setting has no effect. When the gain constant is 0, 1, -1, or a power of 2, the generated code does not use a m

Last post by mamorani « Fri Mar 12, 2021 11:45 am

by mamorani » Fri Mar 12, 2021 11:45 am

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136 Views

Last post by mamorani
Fri Mar 12, 2021 11:45 am
DSPStyle setting has no effect because your synthesis tool is either unspecified or not supported. To use the DSPStyle o

Last post by mamorani « Fri Mar 12, 2021 11:44 am

by mamorani » Fri Mar 12, 2021 11:44 am

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153 Views

Last post by mamorani
Fri Mar 12, 2021 11:44 am
DSPStyle setting has no effect. You cannot apply the DSPStyle option to blocks with one or more 1-bit inputs because the

Last post by mamorani « Fri Mar 12, 2021 11:44 am

by mamorani » Fri Mar 12, 2021 11:44 am

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152 Views

Last post by mamorani
Fri Mar 12, 2021 11:44 am
Port is nested inside a Resettable subsystem, which is not supported.

Last post by mamorani « Fri Mar 12, 2021 11:43 am

by mamorani » Fri Mar 12, 2021 11:43 am

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169 Views

Last post by mamorani
Fri Mar 12, 2021 11:43 am
Cosimulation with Cadence Incisive is not supported with target-specific code generation (floating point support)

Last post by mamorani « Fri Mar 12, 2021 11:42 am

by mamorani » Fri Mar 12, 2021 11:42 am

0 Replies

162 Views

Last post by mamorani
Fri Mar 12, 2021 11:42 am
The control input should not be of floating-point type for target-specific code generation. To use floating point types

Last post by mamorani « Fri Mar 12, 2021 11:42 am

by mamorani » Fri Mar 12, 2021 11:42 am

0 Replies

157 Views

Last post by mamorani
Fri Mar 12, 2021 11:42 am
The block does not permit continuous sample time for HDL code generation. Please use discrete sample time

Last post by mamorani « Fri Mar 12, 2021 11:41 am

by mamorani » Fri Mar 12, 2021 11:41 am

0 Replies

230 Views

Last post by mamorani
Fri Mar 12, 2021 11:41 am
DSPStyle setting has no effect because ConstMultiplierOptimization is set to To use the DSPStyle option, set ConstMultip

Last post by mamorani « Fri Mar 12, 2021 11:41 am

by mamorani » Fri Mar 12, 2021 11:41 am

0 Replies

160 Views

Last post by mamorani
Fri Mar 12, 2021 11:41 am
Complex data-type is unsupported for target-specific code generation.

Last post by mamorani « Fri Mar 12, 2021 11:41 am

by mamorani » Fri Mar 12, 2021 11:41 am

0 Replies

150 Views

Last post by mamorani
Fri Mar 12, 2021 11:41 am
Math Function block with function type ' is not valid for the implementation of ComplexConjugate

Last post by mamorani « Fri Mar 12, 2021 11:40 am

by mamorani » Fri Mar 12, 2021 11:40 am

0 Replies

163 Views

Last post by mamorani
Fri Mar 12, 2021 11:40 am
Math Function block (as Complex Conjugate) with floating point data types is supported only in native floating-point mod

Last post by mamorani « Fri Mar 12, 2021 11:40 am

by mamorani » Fri Mar 12, 2021 11:40 am

0 Replies

145 Views

Last post by mamorani
Fri Mar 12, 2021 11:40 am
Delay block ' with enable port must have a nonzero delay length.

Last post by mamorani « Fri Mar 12, 2021 11:39 am

by mamorani » Fri Mar 12, 2021 11:39 am

0 Replies

149 Views

Last post by mamorani
Fri Mar 12, 2021 11:39 am
Reset port is nested inside another resettable subsystem, which is not supported.

Last post by mamorani « Fri Mar 12, 2021 11:39 am

by mamorani » Fri Mar 12, 2021 11:39 am

0 Replies

146 Views

Last post by mamorani
Fri Mar 12, 2021 11:39 am
Cannot find valid sample time for clock request from block Please ensure that the block has a valid discrete sample tim

Last post by mamorani « Fri Mar 12, 2021 11:38 am

by mamorani » Fri Mar 12, 2021 11:38 am

0 Replies

159 Views

Last post by mamorani
Fri Mar 12, 2021 11:38 am
The input to the Bus Selector block must be a bus signal for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 11:37 am

by mamorani » Fri Mar 12, 2021 11:37 am

0 Replies

144 Views

Last post by mamorani
Fri Mar 12, 2021 11:37 am

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