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Mask Parameter Partitioning option in the For Each Subsystem block, , is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 11:59 am

by mamorani » Fri Mar 12, 2021 11:59 am

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Last post by mamorani
Fri Mar 12, 2021 11:59 am
The For Each Subsystem block, , cannot be used as a DUT for HDL code generation. To generate code for this block, place

Last post by mamorani « Fri Mar 12, 2021 11:59 am

by mamorani » Fri Mar 12, 2021 11:59 am

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Last post by mamorani
Fri Mar 12, 2021 11:59 am
A decimation factor of 1 is not supported for HDL code generation; please use a non-multirate filter instead

Last post by mamorani « Fri Mar 12, 2021 11:57 am

by mamorani » Fri Mar 12, 2021 11:57 am

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317 Views

Last post by mamorani
Fri Mar 12, 2021 11:57 am
All sample times for the FIFO block must be discrete.\nContinuous sample time is not allowed.

Last post by mamorani « Fri Mar 12, 2021 11:56 am

by mamorani » Fri Mar 12, 2021 11:56 am

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290 Views

Last post by mamorani
Fri Mar 12, 2021 11:56 am
HDL FIFO control inputs ''Pop'' and ''Push'' must be Boolean or Ufix1

Last post by mamorani « Fri Mar 12, 2021 11:56 am

by mamorani » Fri Mar 12, 2021 11:56 am

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265 Views

Last post by mamorani
Fri Mar 12, 2021 11:56 am
The HDL FIFO ''In'' and ''Push'' inputs sample times have to be times of the 'Pop' input sample time.

Last post by mamorani « Fri Mar 12, 2021 11:56 am

by mamorani » Fri Mar 12, 2021 11:56 am

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Last post by mamorani
Fri Mar 12, 2021 11:56 am
HDL FIFO supports floating point data input only when native floating-point mode is enabled

Last post by mamorani « Fri Mar 12, 2021 11:55 am

by mamorani » Fri Mar 12, 2021 11:55 am

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261 Views

Last post by mamorani
Fri Mar 12, 2021 11:55 am
HDL FFT only supports transform sizes between 2^3 to 2^17.

Last post by mamorani « Fri Mar 12, 2021 11:55 am

by mamorani » Fri Mar 12, 2021 11:55 am

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232 Views

Last post by mamorani
Fri Mar 12, 2021 11:55 am
The FFT length in HDL Streaming FFT block must be a power of 2, in the range from 2^3 to 2^16

Last post by mamorani « Fri Mar 12, 2021 11:55 am

by mamorani » Fri Mar 12, 2021 11:55 am

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255 Views

Last post by mamorani
Fri Mar 12, 2021 11:55 am
Valid external reset modes are ''none'', ''level'', ''rising'', and ''falling'' for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 11:54 am

by mamorani » Fri Mar 12, 2021 11:54 am

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295 Views

Last post by mamorani
Fri Mar 12, 2021 11:54 am
External initial conditions are not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 11:54 am

by mamorani » Fri Mar 12, 2021 11:54 am

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245 Views

Last post by mamorani
Fri Mar 12, 2021 11:54 am
Invalid model name ' for ' Simulink model name must follow MATLAB variable naming standard. For more information, type

Last post by mamorani « Fri Mar 12, 2021 11:54 am

by mamorani » Fri Mar 12, 2021 11:54 am

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240 Views

Last post by mamorani
Fri Mar 12, 2021 11:54 am
When the external reset is ''rising'' or ''falling'', the initial condition setting must be set to ''State'

Last post by mamorani « Fri Mar 12, 2021 11:53 am

by mamorani » Fri Mar 12, 2021 11:53 am

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260 Views

Last post by mamorani
Fri Mar 12, 2021 11:53 am
The top design unit selected for HDL code generation may not be inside a triggered subsystem

Last post by mamorani « Fri Mar 12, 2021 11:53 am

by mamorani » Fri Mar 12, 2021 11:53 am

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244 Views

Last post by mamorani
Fri Mar 12, 2021 11:53 am
Write access on either or both ports A and B to the same memory address is not supported due to undefined result in the

Last post by mamorani « Fri Mar 12, 2021 11:53 am

by mamorani » Fri Mar 12, 2021 11:53 am

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255 Views

Last post by mamorani
Fri Mar 12, 2021 11:53 am
The address ports of each ports bank are driven by the same signal. Possibility of undefined result in the synthesized R

Last post by mamorani « Fri Mar 12, 2021 11:52 am

by mamorani » Fri Mar 12, 2021 11:52 am

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262 Views

Last post by mamorani
Fri Mar 12, 2021 11:52 am
All ' ports of Dual-rate Dual-port RAM block must have same rate

Last post by mamorani « Fri Mar 12, 2021 11:52 am

by mamorani » Fri Mar 12, 2021 11:52 am

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261 Views

Last post by mamorani
Fri Mar 12, 2021 11:52 am
The Dual Rate Dual Port RAM block does not support mixed real-value and complex inputs.

Last post by mamorani « Fri Mar 12, 2021 11:52 am

by mamorani » Fri Mar 12, 2021 11:52 am

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251 Views

Last post by mamorani
Fri Mar 12, 2021 11:52 am
Inputs to block have mixed vector orientation. To continue code generation, use a Math Function block ''transpose'' op

Last post by mamorani « Fri Mar 12, 2021 11:51 am

by mamorani » Fri Mar 12, 2021 11:51 am

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237 Views

Last post by mamorani
Fri Mar 12, 2021 11:51 am
Input 1 to block is complex with unsigned data type. To generate HDL code, if Input 1 to a Dot Product block is complex

Last post by mamorani « Fri Mar 12, 2021 11:51 am

by mamorani » Fri Mar 12, 2021 11:51 am

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246 Views

Last post by mamorani
Fri Mar 12, 2021 11:51 am
Unable to map Division block to Altera FP IP. Consider using Native Floating Point mode instead

Last post by mamorani « Fri Mar 12, 2021 11:50 am

by mamorani » Fri Mar 12, 2021 11:50 am

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243 Views

Last post by mamorani
Fri Mar 12, 2021 11:50 am
Direct Lookup Table block has a port of enumerated type, which is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 11:50 am

by mamorani » Fri Mar 12, 2021 11:50 am

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234 Views

Last post by mamorani
Fri Mar 12, 2021 11:50 am
HDL code generation for the block does not support out-of-range inputs. Set the "Diagnostic for out of range input" bl

Last post by mamorani « Fri Mar 12, 2021 11:50 am

by mamorani » Fri Mar 12, 2021 11:50 am

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263 Views

Last post by mamorani
Fri Mar 12, 2021 11:50 am
The HDL Streaming FFT block will be removed in a future release. Use the FFT HDL Optimized block in the DSP System Toolb

Last post by mamorani « Fri Mar 12, 2021 11:49 am

by mamorani » Fri Mar 12, 2021 11:49 am

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259 Views

Last post by mamorani
Fri Mar 12, 2021 11:49 am
Cannot find valid sample time for clock request from block. Please ensure that the block has a valid discrete sample tim

Last post by mamorani « Fri Mar 12, 2021 11:49 am

by mamorani » Fri Mar 12, 2021 11:49 am

0 Replies

243 Views

Last post by mamorani
Fri Mar 12, 2021 11:49 am

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