Signal Processing

New Topic

3049 topics

Page 71 of 122
- Jump to page:
Previous
1
…
69
70
71
72
73
…
122
Next

Topics

Replies

Views

Last post

Unable to map Division block to Altera FP IP. Consider using Native Floating Point mode instead.

Last post by mamorani « Fri Mar 12, 2021 1:18 pm

by mamorani » Fri Mar 12, 2021 1:18 pm

0 Replies

272 Views

Last post by mamorani
Fri Mar 12, 2021 1:18 pm
Direct Lookup Table block has a port ' of enumerated type, which is not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 1:18 pm

by mamorani » Fri Mar 12, 2021 1:18 pm

0 Replies

248 Views

Last post by mamorani
Fri Mar 12, 2021 1:18 pm
HDL code generation only supports the ''CORDIC'' Approximation method for block

Last post by mamorani « Fri Mar 12, 2021 12:12 pm

by mamorani » Fri Mar 12, 2021 12:12 pm

0 Replies

226 Views

Last post by mamorani
Fri Mar 12, 2021 12:12 pm
HDL code generation for block ' with fixed-point data supports only the ''ShiftAdd'' architecture. To generate code with

Last post by mamorani « Fri Mar 12, 2021 12:12 pm

by mamorani » Fri Mar 12, 2021 12:12 pm

0 Replies

339 Views

Last post by mamorani
Fri Mar 12, 2021 12:12 pm
Inherit via internal rule'' mode is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 12:11 pm

by mamorani » Fri Mar 12, 2021 12:11 pm

0 Replies

236 Views

Last post by mamorani
Fri Mar 12, 2021 12:11 pm
Integer delays can be mapped to RAMs only when ''Show enable port'' is unchecked. This Delay will not be mapped to a RAM

Last post by mamorani « Fri Mar 12, 2021 12:10 pm

by mamorani » Fri Mar 12, 2021 12:10 pm

0 Replies

208 Views

Last post by mamorani
Fri Mar 12, 2021 12:10 pm
The initial condition for the Delay block must be specified via Dialog.

Last post by mamorani « Fri Mar 12, 2021 12:10 pm

by mamorani » Fri Mar 12, 2021 12:10 pm

0 Replies

231 Views

Last post by mamorani
Fri Mar 12, 2021 12:10 pm
The reset port of the Delay block must have a boolean or ufix1 type.

Last post by mamorani « Fri Mar 12, 2021 12:09 pm

by mamorani » Fri Mar 12, 2021 12:09 pm

0 Replies

200 Views

Last post by mamorani
Fri Mar 12, 2021 12:09 pm
The delay length for the Delay block must be specified via Dialog

Last post by mamorani « Fri Mar 12, 2021 12:09 pm

by mamorani » Fri Mar 12, 2021 12:09 pm

0 Replies

201 Views

Last post by mamorani
Fri Mar 12, 2021 12:09 pm
has an input format of which does not match the requested input format of . Please modify one or the other to match

Last post by mamorani « Fri Mar 12, 2021 12:09 pm

by mamorani » Fri Mar 12, 2021 12:09 pm

0 Replies

174 Views

Last post by mamorani
Fri Mar 12, 2021 12:09 pm
Input cannot be of unsigned type for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 12:08 pm

by mamorani » Fri Mar 12, 2021 12:08 pm

0 Replies

204 Views

Last post by mamorani
Fri Mar 12, 2021 12:08 pm
In order to generate code for a Model block, the optimization configuration parameter should be set to ''Inlined'' for

Last post by mamorani « Fri Mar 12, 2021 12:07 pm

by mamorani » Fri Mar 12, 2021 12:07 pm

0 Replies

187 Views

Last post by mamorani
Fri Mar 12, 2021 12:07 pm
Inline VHDL configurations have been disabled. The generated VHDL code may require an externally supplied Configuration

Last post by mamorani « Fri Mar 12, 2021 12:06 pm

by mamorani » Fri Mar 12, 2021 12:06 pm

0 Replies

244 Views

Last post by mamorani
Fri Mar 12, 2021 12:06 pm
The cascade implementation of the Sum block does not allow Constant(Inf) input sample time.

Last post by mamorani « Fri Mar 12, 2021 12:06 pm

by mamorani » Fri Mar 12, 2021 12:06 pm

0 Replies

230 Views

Last post by mamorani
Fri Mar 12, 2021 12:06 pm
Port indexing should not be of floating-point type for target-specific code generation. To use floating point types on t

Last post by mamorani « Fri Mar 12, 2021 12:05 pm

by mamorani » Fri Mar 12, 2021 12:05 pm

0 Replies

265 Views

Last post by mamorani
Fri Mar 12, 2021 12:05 pm
Unsupported intermediate data type in RecipSqrtNewton

Last post by mamorani « Fri Mar 12, 2021 12:05 pm

by mamorani » Fri Mar 12, 2021 12:05 pm

0 Replies

222 Views

Last post by mamorani
Fri Mar 12, 2021 12:05 pm
When input of Discrete Transfer Fcn block is floating point, all the internal data-type should be inherited to support H

Last post by mamorani « Fri Mar 12, 2021 12:04 pm

by mamorani » Fri Mar 12, 2021 12:04 pm

0 Replies

245 Views

Last post by mamorani
Fri Mar 12, 2021 12:04 pm
Only ''u2 ~= 0'' criteria is supported for target-specific code generation. Consider selecting ''Native Floating Point''

Last post by mamorani « Fri Mar 12, 2021 12:04 pm

by mamorani » Fri Mar 12, 2021 12:04 pm

0 Replies

241 Views

Last post by mamorani
Fri Mar 12, 2021 12:04 pm
Both input and output types for block ' should be of the same floating-point type for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 12:03 pm

by mamorani » Fri Mar 12, 2021 12:03 pm

0 Replies

223 Views

Last post by mamorani
Fri Mar 12, 2021 12:03 pm
HitCross direction mode ''either'' is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 12:03 pm

by mamorani » Fri Mar 12, 2021 12:03 pm

0 Replies

244 Views

Last post by mamorani
Fri Mar 12, 2021 12:03 pm
Expected block to have only a single rate but more than one was found.

Last post by mamorani « Fri Mar 12, 2021 12:02 pm

by mamorani » Fri Mar 12, 2021 12:02 pm

0 Replies

211 Views

Last post by mamorani
Fri Mar 12, 2021 12:02 pm
The ''States when starting'' option on the For Iterator block ' must be set to ''held'' to continue HDL code generation

Last post by mamorani « Fri Mar 12, 2021 12:02 pm

by mamorani » Fri Mar 12, 2021 12:02 pm

0 Replies

243 Views

Last post by mamorani
Fri Mar 12, 2021 12:02 pm
The ''Iteration limit source'' option on the For Iterator block ' must be set to ''internal'' to continue HDL code gener

Last post by mamorani « Fri Mar 12, 2021 12:01 pm

by mamorani » Fri Mar 12, 2021 12:01 pm

0 Replies

219 Views

Last post by mamorani
Fri Mar 12, 2021 12:01 pm
The ''Set next i (iteration variable) externally'' check box on the For Iterator block must be cleared to continue HDL

Last post by mamorani « Fri Mar 12, 2021 12:00 pm

by mamorani » Fri Mar 12, 2021 12:00 pm

0 Replies

202 Views

Last post by mamorani
Fri Mar 12, 2021 12:00 pm
The For Iterator Subsystem block, , cannot be used as a DUT for HDL code generation. To generate code for this block, pl

Last post by mamorani « Fri Mar 12, 2021 12:00 pm

by mamorani » Fri Mar 12, 2021 12:00 pm

0 Replies

244 Views

Last post by mamorani
Fri Mar 12, 2021 12:00 pm

New Topic

3049 topics

Page 71 of 122
- Jump to page:
Previous
1
…
69
70
71
72
73
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 2 guests

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum