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Unable to map Division block to Altera FP IP. Consider using Native Floating Point mode instead.

Last post by mamorani « Fri Mar 12, 2021 1:18 pm

by mamorani » Fri Mar 12, 2021 1:18 pm

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310 Views

Last post by mamorani
Fri Mar 12, 2021 1:18 pm
Direct Lookup Table block has a port ' of enumerated type, which is not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 1:18 pm

by mamorani » Fri Mar 12, 2021 1:18 pm

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296 Views

Last post by mamorani
Fri Mar 12, 2021 1:18 pm
HDL code generation only supports the ''CORDIC'' Approximation method for block

Last post by mamorani « Fri Mar 12, 2021 12:12 pm

by mamorani » Fri Mar 12, 2021 12:12 pm

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274 Views

Last post by mamorani
Fri Mar 12, 2021 12:12 pm
HDL code generation for block ' with fixed-point data supports only the ''ShiftAdd'' architecture. To generate code with

Last post by mamorani « Fri Mar 12, 2021 12:12 pm

by mamorani » Fri Mar 12, 2021 12:12 pm

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387 Views

Last post by mamorani
Fri Mar 12, 2021 12:12 pm
Inherit via internal rule'' mode is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 12:11 pm

by mamorani » Fri Mar 12, 2021 12:11 pm

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284 Views

Last post by mamorani
Fri Mar 12, 2021 12:11 pm
Integer delays can be mapped to RAMs only when ''Show enable port'' is unchecked. This Delay will not be mapped to a RAM

Last post by mamorani « Fri Mar 12, 2021 12:10 pm

by mamorani » Fri Mar 12, 2021 12:10 pm

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252 Views

Last post by mamorani
Fri Mar 12, 2021 12:10 pm
The initial condition for the Delay block must be specified via Dialog.

Last post by mamorani « Fri Mar 12, 2021 12:10 pm

by mamorani » Fri Mar 12, 2021 12:10 pm

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281 Views

Last post by mamorani
Fri Mar 12, 2021 12:10 pm
The reset port of the Delay block must have a boolean or ufix1 type.

Last post by mamorani « Fri Mar 12, 2021 12:09 pm

by mamorani » Fri Mar 12, 2021 12:09 pm

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245 Views

Last post by mamorani
Fri Mar 12, 2021 12:09 pm
The delay length for the Delay block must be specified via Dialog

Last post by mamorani « Fri Mar 12, 2021 12:09 pm

by mamorani » Fri Mar 12, 2021 12:09 pm

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246 Views

Last post by mamorani
Fri Mar 12, 2021 12:09 pm
has an input format of which does not match the requested input format of . Please modify one or the other to match

Last post by mamorani « Fri Mar 12, 2021 12:09 pm

by mamorani » Fri Mar 12, 2021 12:09 pm

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217 Views

Last post by mamorani
Fri Mar 12, 2021 12:09 pm
Input cannot be of unsigned type for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 12:08 pm

by mamorani » Fri Mar 12, 2021 12:08 pm

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248 Views

Last post by mamorani
Fri Mar 12, 2021 12:08 pm
In order to generate code for a Model block, the optimization configuration parameter should be set to ''Inlined'' for

Last post by mamorani « Fri Mar 12, 2021 12:07 pm

by mamorani » Fri Mar 12, 2021 12:07 pm

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231 Views

Last post by mamorani
Fri Mar 12, 2021 12:07 pm
Inline VHDL configurations have been disabled. The generated VHDL code may require an externally supplied Configuration

Last post by mamorani « Fri Mar 12, 2021 12:06 pm

by mamorani » Fri Mar 12, 2021 12:06 pm

0 Replies

288 Views

Last post by mamorani
Fri Mar 12, 2021 12:06 pm
The cascade implementation of the Sum block does not allow Constant(Inf) input sample time.

Last post by mamorani « Fri Mar 12, 2021 12:06 pm

by mamorani » Fri Mar 12, 2021 12:06 pm

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273 Views

Last post by mamorani
Fri Mar 12, 2021 12:06 pm
Port indexing should not be of floating-point type for target-specific code generation. To use floating point types on t

Last post by mamorani « Fri Mar 12, 2021 12:05 pm

by mamorani » Fri Mar 12, 2021 12:05 pm

0 Replies

317 Views

Last post by mamorani
Fri Mar 12, 2021 12:05 pm
Unsupported intermediate data type in RecipSqrtNewton

Last post by mamorani « Fri Mar 12, 2021 12:05 pm

by mamorani » Fri Mar 12, 2021 12:05 pm

0 Replies

262 Views

Last post by mamorani
Fri Mar 12, 2021 12:05 pm
When input of Discrete Transfer Fcn block is floating point, all the internal data-type should be inherited to support H

Last post by mamorani « Fri Mar 12, 2021 12:04 pm

by mamorani » Fri Mar 12, 2021 12:04 pm

0 Replies

287 Views

Last post by mamorani
Fri Mar 12, 2021 12:04 pm
Only ''u2 ~= 0'' criteria is supported for target-specific code generation. Consider selecting ''Native Floating Point''

Last post by mamorani « Fri Mar 12, 2021 12:04 pm

by mamorani » Fri Mar 12, 2021 12:04 pm

0 Replies

286 Views

Last post by mamorani
Fri Mar 12, 2021 12:04 pm
Both input and output types for block ' should be of the same floating-point type for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 12:03 pm

by mamorani » Fri Mar 12, 2021 12:03 pm

0 Replies

271 Views

Last post by mamorani
Fri Mar 12, 2021 12:03 pm
HitCross direction mode ''either'' is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 12:03 pm

by mamorani » Fri Mar 12, 2021 12:03 pm

0 Replies

285 Views

Last post by mamorani
Fri Mar 12, 2021 12:03 pm
Expected block to have only a single rate but more than one was found.

Last post by mamorani « Fri Mar 12, 2021 12:02 pm

by mamorani » Fri Mar 12, 2021 12:02 pm

0 Replies

258 Views

Last post by mamorani
Fri Mar 12, 2021 12:02 pm
The ''States when starting'' option on the For Iterator block ' must be set to ''held'' to continue HDL code generation

Last post by mamorani « Fri Mar 12, 2021 12:02 pm

by mamorani » Fri Mar 12, 2021 12:02 pm

0 Replies

287 Views

Last post by mamorani
Fri Mar 12, 2021 12:02 pm
The ''Iteration limit source'' option on the For Iterator block ' must be set to ''internal'' to continue HDL code gener

Last post by mamorani « Fri Mar 12, 2021 12:01 pm

by mamorani » Fri Mar 12, 2021 12:01 pm

0 Replies

267 Views

Last post by mamorani
Fri Mar 12, 2021 12:01 pm
The ''Set next i (iteration variable) externally'' check box on the For Iterator block must be cleared to continue HDL

Last post by mamorani « Fri Mar 12, 2021 12:00 pm

by mamorani » Fri Mar 12, 2021 12:00 pm

0 Replies

245 Views

Last post by mamorani
Fri Mar 12, 2021 12:00 pm
The For Iterator Subsystem block, , cannot be used as a DUT for HDL code generation. To generate code for this block, pl

Last post by mamorani « Fri Mar 12, 2021 12:00 pm

by mamorani » Fri Mar 12, 2021 12:00 pm

0 Replies

294 Views

Last post by mamorani
Fri Mar 12, 2021 12:00 pm

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