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Both input and output types for block should be of the same floating-point type for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 1:35 pm

by mamorani » Fri Mar 12, 2021 1:35 pm

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206 Views

Last post by mamorani
Fri Mar 12, 2021 1:35 pm
HitCross direction mode ''either'' is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 1:33 pm

by mamorani » Fri Mar 12, 2021 1:33 pm

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210 Views

Last post by mamorani
Fri Mar 12, 2021 1:33 pm
Expected block to have only a single rate but more than one was found.

Last post by mamorani « Fri Mar 12, 2021 1:32 pm

by mamorani » Fri Mar 12, 2021 1:32 pm

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190 Views

Last post by mamorani
Fri Mar 12, 2021 1:32 pm
The For Iterator Subsystem must have at least one input or output port to continue HDL code generation

Last post by mamorani « Fri Mar 12, 2021 1:31 pm

by mamorani » Fri Mar 12, 2021 1:31 pm

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202 Views

Last post by mamorani
Fri Mar 12, 2021 1:31 pm
The ''Set next i (iteration variable) externally'' check box on the For Iterator block must be cleared to continue HDL

Last post by mamorani « Fri Mar 12, 2021 1:30 pm

by mamorani » Fri Mar 12, 2021 1:30 pm

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246 Views

Last post by mamorani
Fri Mar 12, 2021 1:30 pm
The For Iterator Subsystem block, , cannot be used as a DUT for HDL code generation. To generate code for this block, p

Last post by mamorani « Fri Mar 12, 2021 1:30 pm

by mamorani » Fri Mar 12, 2021 1:30 pm

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208 Views

Last post by mamorani
Fri Mar 12, 2021 1:30 pm
Mask Parameter Partitioning option in the For Each Subsystem block, is not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 1:29 pm

by mamorani » Fri Mar 12, 2021 1:29 pm

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267 Views

Last post by mamorani
Fri Mar 12, 2021 1:29 pm
The For Each Subsystem block, ' cannot be used as a DUT for HDL code generation. To generate code for this block, place

Last post by mamorani « Fri Mar 12, 2021 1:28 pm

by mamorani » Fri Mar 12, 2021 1:28 pm

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212 Views

Last post by mamorani
Fri Mar 12, 2021 1:28 pm
A decimation factor of 1 is not supported for HDL code generation; please use a non-multirate filter instead

Last post by mamorani « Fri Mar 12, 2021 1:28 pm

by mamorani » Fri Mar 12, 2021 1:28 pm

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199 Views

Last post by mamorani
Fri Mar 12, 2021 1:28 pm
All sample times for the FIFO block must be discrete.\nContinuous sample time is not allowed

Last post by mamorani « Fri Mar 12, 2021 1:26 pm

by mamorani » Fri Mar 12, 2021 1:26 pm

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217 Views

Last post by mamorani
Fri Mar 12, 2021 1:26 pm
HDL FIFO control inputs ''Pop'' and ''Push'' must be Boolean or Ufix1

Last post by mamorani « Fri Mar 12, 2021 1:26 pm

by mamorani » Fri Mar 12, 2021 1:26 pm

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197 Views

Last post by mamorani
Fri Mar 12, 2021 1:26 pm
The HDL FIFO ''In'' and ''Push'' inputs sample times have to be times of the 'Pop' input sample time

Last post by mamorani « Fri Mar 12, 2021 1:25 pm

by mamorani » Fri Mar 12, 2021 1:25 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 1:25 pm
HDL FIFO supports floating point data input only when native floating-point mode is enabled

Last post by mamorani « Fri Mar 12, 2021 1:24 pm

by mamorani » Fri Mar 12, 2021 1:24 pm

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231 Views

Last post by mamorani
Fri Mar 12, 2021 1:24 pm
Valid external reset modes are ''none'', ''level'', ''rising'', and ''falling'' for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 1:24 pm

by mamorani » Fri Mar 12, 2021 1:24 pm

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258 Views

Last post by mamorani
Fri Mar 12, 2021 1:24 pm
External initial conditions are not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 1:24 pm

by mamorani » Fri Mar 12, 2021 1:24 pm

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256 Views

Last post by mamorani
Fri Mar 12, 2021 1:24 pm
Invalid model name ' for '. Simulink model name must follow MATLAB variable naming standard. For more information, type

Last post by mamorani « Fri Mar 12, 2021 1:23 pm

by mamorani » Fri Mar 12, 2021 1:23 pm

0 Replies

237 Views

Last post by mamorani
Fri Mar 12, 2021 1:23 pm
When the external reset is ''rising'' or ''falling'', the initial condition setting must be set to ''State'

Last post by mamorani « Fri Mar 12, 2021 1:23 pm

by mamorani » Fri Mar 12, 2021 1:23 pm

0 Replies

277 Views

Last post by mamorani
Fri Mar 12, 2021 1:23 pm
The top design unit selected for HDL code generation may not be inside a triggered subsystem

Last post by mamorani « Fri Mar 12, 2021 1:22 pm

by mamorani » Fri Mar 12, 2021 1:22 pm

0 Replies

232 Views

Last post by mamorani
Fri Mar 12, 2021 1:22 pm
Write access on either or both ports A and B to the same memory address is not supported due to undefined result in the

Last post by mamorani « Fri Mar 12, 2021 1:22 pm

by mamorani » Fri Mar 12, 2021 1:22 pm

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240 Views

Last post by mamorani
Fri Mar 12, 2021 1:22 pm
The address ports of each ports bank are driven by the same signal. Possibility of undefined result in the synthesized R

Last post by mamorani « Fri Mar 12, 2021 1:22 pm

by mamorani » Fri Mar 12, 2021 1:22 pm

0 Replies

217 Views

Last post by mamorani
Fri Mar 12, 2021 1:22 pm
All ' ports of Dual-rate Dual-port RAM block must have same rate.

Last post by mamorani « Fri Mar 12, 2021 1:22 pm

by mamorani » Fri Mar 12, 2021 1:22 pm

0 Replies

242 Views

Last post by mamorani
Fri Mar 12, 2021 1:22 pm
The Dual Rate Dual Port RAM block does not support mixed real-value and complex inputs.

Last post by mamorani « Fri Mar 12, 2021 1:21 pm

by mamorani » Fri Mar 12, 2021 1:21 pm

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251 Views

Last post by mamorani
Fri Mar 12, 2021 1:21 pm
The Dual Rate Dual Port RAM block does not support mixed real-value and complex inputs.

Last post by mamorani « Fri Mar 12, 2021 1:21 pm

by mamorani » Fri Mar 12, 2021 1:21 pm

0 Replies

226 Views

Last post by mamorani
Fri Mar 12, 2021 1:21 pm
Inputs to block have mixed vector orientation. To continue code generation, use a Math Function block ''transpose'' ope

Last post by mamorani « Fri Mar 12, 2021 1:21 pm

by mamorani » Fri Mar 12, 2021 1:21 pm

0 Replies

255 Views

Last post by mamorani
Fri Mar 12, 2021 1:21 pm
Input 1 to block is complex with unsigned data type. To generate HDL code, if Input 1 to a Dot Product block is comple

Last post by mamorani « Fri Mar 12, 2021 1:20 pm

by mamorani » Fri Mar 12, 2021 1:20 pm

0 Replies

251 Views

Last post by mamorani
Fri Mar 12, 2021 1:20 pm

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