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HDL code generation for the multichannel FIR is only supported for sample based input processing

Last post by mamorani « Fri Mar 12, 2021 3:33 pm

by mamorani » Fri Mar 12, 2021 3:33 pm

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Last post by mamorani
Fri Mar 12, 2021 3:33 pm
Multichannel implementation is only supported for Fully Parallel architecture.

Last post by mamorani « Fri Mar 12, 2021 3:32 pm

by mamorani » Fri Mar 12, 2021 3:32 pm

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392 Views

Last post by mamorani
Fri Mar 12, 2021 3:32 pm
Sum block with tree implementation does not support the subtract operation.

Last post by mamorani « Fri Mar 12, 2021 3:31 pm

by mamorani » Fri Mar 12, 2021 3:31 pm

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240 Views

Last post by mamorani
Fri Mar 12, 2021 3:31 pm
This block is not supported for Xilinx Coregen mapping

Last post by mamorani « Fri Mar 12, 2021 3:31 pm

by mamorani » Fri Mar 12, 2021 3:31 pm

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277 Views

Last post by mamorani
Fri Mar 12, 2021 3:31 pm
This block is not supported for Altera Megafunction mapping.

Last post by mamorani « Fri Mar 12, 2021 3:31 pm

by mamorani » Fri Mar 12, 2021 3:31 pm

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243 Views

Last post by mamorani
Fri Mar 12, 2021 3:31 pm
Unsupported filter in block IIR SOS and FIR filters are supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 3:30 pm

by mamorani » Fri Mar 12, 2021 3:30 pm

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241 Views

Last post by mamorani
Fri Mar 12, 2021 3:30 pm
Unsupported FIR filter structure in block Supported structures are: Direct form, Direct form symmetric, Direct form an

Last post by mamorani « Fri Mar 12, 2021 3:30 pm

by mamorani » Fri Mar 12, 2021 3:30 pm

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245 Views

Last post by mamorani
Fri Mar 12, 2021 3:30 pm
The '' port for the block ' must be a scalar boolean type for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 3:29 pm

by mamorani » Fri Mar 12, 2021 3:29 pm

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244 Views

Last post by mamorani
Fri Mar 12, 2021 3:29 pm
A vector of buses is not supported. If you intended to expand buses with identically typed elements into a vector, first

Last post by mamorani « Fri Mar 12, 2021 3:29 pm

by mamorani » Fri Mar 12, 2021 3:29 pm

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240 Views

Last post by mamorani
Fri Mar 12, 2021 3:29 pm
The Reset port of the Unit Delay Enabled Resettable block, must be a scalar boolean type for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 3:28 pm

by mamorani » Fri Mar 12, 2021 3:28 pm

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287 Views

Last post by mamorani
Fri Mar 12, 2021 3:28 pm
HDL code generation requires ''Boolean'' type for Enable port for the block

Last post by mamorani « Fri Mar 12, 2021 3:27 pm

by mamorani » Fri Mar 12, 2021 3:27 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 3:27 pm
Simulink.Parameter object has not been marked as tunable. Please mark the parameter as ''Tunable'' for HDL code genera

Last post by mamorani « Fri Mar 12, 2021 3:27 pm

by mamorani » Fri Mar 12, 2021 3:27 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 3:27 pm
Tunable parameter ' ' is stored in a non-top level data dictionary and will be routed to the top level of the DUT during

Last post by mamorani « Fri Mar 12, 2021 3:27 pm

by mamorani » Fri Mar 12, 2021 3:27 pm

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325 Views

Last post by mamorani
Fri Mar 12, 2021 3:27 pm
The ''Trigger As Clock'' setting requires the Reset Type to be ''Asynchronous'

Last post by mamorani « Fri Mar 12, 2021 3:26 pm

by mamorani » Fri Mar 12, 2021 3:26 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 3:26 pm
Trigger as Clock is only supported for the same clock edge as HDL Coder is configured for. Trigger port ' has a trigg

Last post by mamorani « Fri Mar 12, 2021 3:21 pm

by mamorani » Fri Mar 12, 2021 3:21 pm

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245 Views

Last post by mamorani
Fri Mar 12, 2021 3:21 pm
Subsystem has both a Trigger port and an Enable port, which is not supported for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 3:21 pm

by mamorani » Fri Mar 12, 2021 3:21 pm

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248 Views

Last post by mamorani
Fri Mar 12, 2021 3:21 pm
The HDL implementation ''TrigonometricTargetLibrary'' set on this block is relevant only for target-specific code genera

Last post by mamorani « Fri Mar 12, 2021 3:20 pm

by mamorani » Fri Mar 12, 2021 3:20 pm

0 Replies

272 Views

Last post by mamorani
Fri Mar 12, 2021 3:20 pm
Math Function block ' with function type ' ' is not valid for the implementation Transpose

Last post by mamorani « Fri Mar 12, 2021 3:20 pm

by mamorani » Fri Mar 12, 2021 3:20 pm

0 Replies

243 Views

Last post by mamorani
Fri Mar 12, 2021 3:20 pm
HDL code generation is not directly supported for a This object must be enclosed within a subsystem.

Last post by mamorani « Fri Mar 12, 2021 3:19 pm

by mamorani » Fri Mar 12, 2021 3:19 pm

0 Replies

250 Views

Last post by mamorani
Fri Mar 12, 2021 3:19 pm
Product block with tree or cascade implementation requires a single vector as input

Last post by mamorani « Fri Mar 12, 2021 3:19 pm

by mamorani » Fri Mar 12, 2021 3:19 pm

0 Replies

240 Views

Last post by mamorani
Fri Mar 12, 2021 3:19 pm
Sum block with tree implementation requires a single vector as input

Last post by mamorani « Fri Mar 12, 2021 3:18 pm

by mamorani » Fri Mar 12, 2021 3:18 pm

0 Replies

259 Views

Last post by mamorani
Fri Mar 12, 2021 3:18 pm
Block with cascade implementation requires a single vector as input.

Last post by mamorani « Fri Mar 12, 2021 3:18 pm

by mamorani » Fri Mar 12, 2021 3:18 pm

0 Replies

258 Views

Last post by mamorani
Fri Mar 12, 2021 3:18 pm
Target device must be specified to generate Xilinx LogiCORE IPs. Specify the device in the 'HDL Code Generation -> Targe

Last post by mamorani « Fri Mar 12, 2021 3:18 pm

by mamorani » Fri Mar 12, 2021 3:18 pm

0 Replies

269 Views

Last post by mamorani
Fri Mar 12, 2021 3:18 pm
The data type should be double or single for target-specific code generation.

Last post by mamorani « Fri Mar 12, 2021 3:17 pm

by mamorani » Fri Mar 12, 2021 3:17 pm

0 Replies

251 Views

Last post by mamorani
Fri Mar 12, 2021 3:17 pm
The HDL implementation ''MathTargetLibrary'' set on this block is relevant only for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 3:17 pm

by mamorani » Fri Mar 12, 2021 3:17 pm

0 Replies

258 Views

Last post by mamorani
Fri Mar 12, 2021 3:17 pm

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