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Threshold setting and control signal input must be of equal size for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 3:44 pm

by mamorani » Fri Mar 12, 2021 3:44 pm

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Last post by mamorani
Fri Mar 12, 2021 3:44 pm
Linear Interpolation is not supported with complex table data by the Lookup Table (n-D) block for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 3:44 pm

by mamorani » Fri Mar 12, 2021 3:44 pm

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210 Views

Last post by mamorani
Fri Mar 12, 2021 3:44 pm
Wrong number of clock ports found in cosimulation block

Last post by mamorani « Fri Mar 12, 2021 3:44 pm

by mamorani » Fri Mar 12, 2021 3:44 pm

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196 Views

Last post by mamorani
Fri Mar 12, 2021 3:44 pm
The "Process out-of-range input" parameter on the Prelookup block must be set to "Clip to range" for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 3:43 pm

by mamorani » Fri Mar 12, 2021 3:43 pm

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204 Views

Last post by mamorani
Fri Mar 12, 2021 3:43 pm
All BusCreator input signals are required to have same rate for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 3:43 pm

by mamorani » Fri Mar 12, 2021 3:43 pm

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224 Views

Last post by mamorani
Fri Mar 12, 2021 3:43 pm
The breakpoint specification for the block must be set to ''Explicit values'' or ''Even spacing'' for HDL code generat

Last post by mamorani « Fri Mar 12, 2021 3:43 pm

by mamorani » Fri Mar 12, 2021 3:43 pm

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209 Views

Last post by mamorani
Fri Mar 12, 2021 3:43 pm
HDL code generation is not supported for this block inside a resettable subsystem

Last post by mamorani « Fri Mar 12, 2021 3:42 pm

by mamorani » Fri Mar 12, 2021 3:42 pm

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217 Views

Last post by mamorani
Fri Mar 12, 2021 3:42 pm
The configuration of the block requires oversampling that violates the MaxOversampling constraint

Last post by mamorani « Fri Mar 12, 2021 3:41 pm

by mamorani » Fri Mar 12, 2021 3:41 pm

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209 Views

Last post by mamorani
Fri Mar 12, 2021 3:41 pm
Port on Model block is a Bus type. This is not supported for a Black Box HDL implementation. Either change the HDL A

Last post by mamorani « Fri Mar 12, 2021 3:41 pm

by mamorani » Fri Mar 12, 2021 3:41 pm

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200 Views

Last post by mamorani
Fri Mar 12, 2021 3:41 pm
Distributed pipelining will not distribute registers inside the logic of this block

Last post by mamorani « Fri Mar 12, 2021 3:41 pm

by mamorani » Fri Mar 12, 2021 3:41 pm

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Last post by mamorani
Fri Mar 12, 2021 3:41 pm
In order to avoid additional type-casting of signals, converting the filter''s setting in [wordlength, fractionlength] f

Last post by mamorani « Fri Mar 12, 2021 3:40 pm

by mamorani » Fri Mar 12, 2021 3:40 pm

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218 Views

Last post by mamorani
Fri Mar 12, 2021 3:40 pm
The Lookup Table (n-D) block does not support an unsigned 128-bit fixed point type.

Last post by mamorani « Fri Mar 12, 2021 3:39 pm

by mamorani » Fri Mar 12, 2021 3:39 pm

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208 Views

Last post by mamorani
Fri Mar 12, 2021 3:39 pm
The control port is an unsigned signal which is always >= Threshold when the Threshold = 0. This block will never switch

Last post by mamorani « Fri Mar 12, 2021 3:39 pm

by mamorani » Fri Mar 12, 2021 3:39 pm

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222 Views

Last post by mamorani
Fri Mar 12, 2021 3:39 pm
Specified HDL code generation system does not exist in model

Last post by mamorani « Fri Mar 12, 2021 3:39 pm

by mamorani » Fri Mar 12, 2021 3:39 pm

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215 Views

Last post by mamorani
Fri Mar 12, 2021 3:39 pm
The XilinxBlackBox parameter will be removed in a future release. Use an Xilinx System Generator Subsystem to integrate

Last post by mamorani « Fri Mar 12, 2021 3:38 pm

by mamorani » Fri Mar 12, 2021 3:38 pm

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214 Views

Last post by mamorani
Fri Mar 12, 2021 3:38 pm
Use of virtual bus inside the model/subsystem hierarchy at resulted in an internal error. Use of non virtual bus inste

Last post by mamorani « Fri Mar 12, 2021 3:37 pm

by mamorani » Fri Mar 12, 2021 3:37 pm

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232 Views

Last post by mamorani
Fri Mar 12, 2021 3:37 pm
HDL code generation does not support a 1-bit vector input datatype when the input is a row vector and min/max is being c

Last post by mamorani « Fri Mar 12, 2021 3:37 pm

by mamorani » Fri Mar 12, 2021 3:37 pm

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211 Views

Last post by mamorani
Fri Mar 12, 2021 3:37 pm
Multi-dimensional signals are not supported in this block for target-specific code generation.

Last post by mamorani « Fri Mar 12, 2021 3:37 pm

by mamorani » Fri Mar 12, 2021 3:37 pm

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208 Views

Last post by mamorani
Fri Mar 12, 2021 3:37 pm
Vector and matrix inputs are not supported for this block.

Last post by mamorani « Fri Mar 12, 2021 3:36 pm

by mamorani » Fri Mar 12, 2021 3:36 pm

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209 Views

Last post by mamorani
Fri Mar 12, 2021 3:36 pm
introduces a delay before the block in the generated model. This may introduce simulation mismatch in the initial cycles

Last post by mamorani « Fri Mar 12, 2021 3:36 pm

by mamorani » Fri Mar 12, 2021 3:36 pm

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192 Views

Last post by mamorani
Fri Mar 12, 2021 3:36 pm
For fixed-point data-type, word-length of less than 4 is unsupported by Xilinx

Last post by mamorani « Fri Mar 12, 2021 3:35 pm

by mamorani » Fri Mar 12, 2021 3:35 pm

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216 Views

Last post by mamorani
Fri Mar 12, 2021 3:35 pm
VHDLFileExtension must be ''.vhd'' for target-specific code generation.

Last post by mamorani « Fri Mar 12, 2021 3:35 pm

by mamorani » Fri Mar 12, 2021 3:35 pm

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248 Views

Last post by mamorani
Fri Mar 12, 2021 3:35 pm
VerilogFileExtension must be ''.v'' for target-specific code generation.

Last post by mamorani « Fri Mar 12, 2021 3:34 pm

by mamorani » Fri Mar 12, 2021 3:34 pm

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243 Views

Last post by mamorani
Fri Mar 12, 2021 3:34 pm
Only ''++'' or ''+-'' sign is supported for floating-point target library mapping.

Last post by mamorani « Fri Mar 12, 2021 3:34 pm

by mamorani » Fri Mar 12, 2021 3:34 pm

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234 Views

Last post by mamorani
Fri Mar 12, 2021 3:34 pm
HDL code generation does not support Mux blocks with bus inputs. Use concatenate block to define array of buses

Last post by mamorani « Fri Mar 12, 2021 3:33 pm

by mamorani » Fri Mar 12, 2021 3:33 pm

0 Replies

242 Views

Last post by mamorani
Fri Mar 12, 2021 3:33 pm

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