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The switch threshold is not representable in selector''s 1-bit selector data type

Last post by mamorani « Fri Mar 12, 2021 8:18 pm

by mamorani » Fri Mar 12, 2021 8:18 pm

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192 Views

Last post by mamorani
Fri Mar 12, 2021 8:18 pm
Specify indices'' mode is only supported when the control port is an enumerated type

Last post by mamorani « Fri Mar 12, 2021 8:18 pm

by mamorani » Fri Mar 12, 2021 8:18 pm

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223 Views

Last post by mamorani
Fri Mar 12, 2021 8:18 pm
Streaming matrix inverse is not supported with Gauss-Jordan elimination algorithm.

Last post by mamorani « Fri Mar 12, 2021 8:17 pm

by mamorani » Fri Mar 12, 2021 8:17 pm

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206 Views

Last post by mamorani
Fri Mar 12, 2021 8:17 pm
Rate Transition block is supported only if 1) both Data Integrity and Deterministic Data Transfer are enabled or 2) both

Last post by mamorani « Fri Mar 12, 2021 8:16 pm

by mamorani » Fri Mar 12, 2021 8:16 pm

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202 Views

Last post by mamorani
Fri Mar 12, 2021 8:16 pm
PID Controller block ' is not supported for HDL target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 8:16 pm

by mamorani » Fri Mar 12, 2021 8:16 pm

0 Replies

199 Views

Last post by mamorani
Fri Mar 12, 2021 8:16 pm
is not supported by the Multi Port Switch block parameter "Data Port Order" for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 8:15 pm

by mamorani » Fri Mar 12, 2021 8:15 pm

0 Replies

193 Views

Last post by mamorani
Fri Mar 12, 2021 8:15 pm
Output signals to bus element ports cannot have different sample time values.

Last post by mamorani « Fri Mar 12, 2021 8:15 pm

by mamorani » Fri Mar 12, 2021 8:15 pm

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196 Views

Last post by mamorani
Fri Mar 12, 2021 8:15 pm
A signed multiply with natural width of > 128 bits cannot have a unsigned 128-bit output type

Last post by mamorani « Fri Mar 12, 2021 8:15 pm

by mamorani » Fri Mar 12, 2021 8:15 pm

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194 Views

Last post by mamorani
Fri Mar 12, 2021 8:15 pm
Slope and Bias Data-types are not supported for HDL Code generation.

Last post by mamorani « Fri Mar 12, 2021 8:14 pm

by mamorani » Fri Mar 12, 2021 8:14 pm

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205 Views

Last post by mamorani
Fri Mar 12, 2021 8:14 pm
Shift signal cannot be a vector; use scalar shift signal for the Shift Arithmetic block

Last post by mamorani « Fri Mar 12, 2021 8:13 pm

by mamorani » Fri Mar 12, 2021 8:13 pm

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200 Views

Last post by mamorani
Fri Mar 12, 2021 8:13 pm
NFPLog2 block is only supported in the native floating-point mode

Last post by mamorani « Fri Mar 12, 2021 8:13 pm

by mamorani » Fri Mar 12, 2021 8:13 pm

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220 Views

Last post by mamorani
Fri Mar 12, 2021 8:13 pm
Math Function block with function type '' ' is not valid for the implementation Hermitian.

Last post by mamorani « Fri Mar 12, 2021 8:12 pm

by mamorani » Fri Mar 12, 2021 8:12 pm

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214 Views

Last post by mamorani
Fri Mar 12, 2021 8:12 pm
Constant matrix'' parameter must be a 2-dimensional or 3-dimensional matrix

Last post by mamorani « Fri Mar 12, 2021 8:11 pm

by mamorani » Fri Mar 12, 2021 8:11 pm

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192 Views

Last post by mamorani
Fri Mar 12, 2021 8:11 pm
Invalid mode used for bit shift component. Supported modes are left and right

Last post by mamorani « Fri Mar 12, 2021 8:10 pm

by mamorani » Fri Mar 12, 2021 8:10 pm

0 Replies

206 Views

Last post by mamorani
Fri Mar 12, 2021 8:10 pm
For HDL code generation, input signal must be an integer or fixed-point data type.

Last post by mamorani « Fri Mar 12, 2021 8:09 pm

by mamorani » Fri Mar 12, 2021 8:09 pm

0 Replies

186 Views

Last post by mamorani
Fri Mar 12, 2021 8:09 pm
Binary point shift is not supported for the two input shift block.

Last post by mamorani « Fri Mar 12, 2021 8:09 pm

by mamorani » Fri Mar 12, 2021 8:09 pm

0 Replies

641 Views

Last post by mamorani
Fri Mar 12, 2021 8:09 pm
Number of bits to shift must be specified through dialog by setting ''Source'' to ''Dialog'

Last post by mamorani « Fri Mar 12, 2021 8:09 pm

by mamorani » Fri Mar 12, 2021 8:09 pm

0 Replies

199 Views

Last post by mamorani
Fri Mar 12, 2021 8:09 pm
Shift Arithmetic block with floating-point input is not supported for HDL code generation. Use a fixed-point or integer

Last post by mamorani « Fri Mar 12, 2021 8:08 pm

by mamorani » Fri Mar 12, 2021 8:08 pm

0 Replies

203 Views

Last post by mamorani
Fri Mar 12, 2021 8:08 pm
Blocks with mixed length vector inputs are not supported in

Last post by mamorani « Fri Mar 12, 2021 8:08 pm

by mamorani » Fri Mar 12, 2021 8:08 pm

0 Replies

206 Views

Last post by mamorani
Fri Mar 12, 2021 8:08 pm
HDL code generation is only supported for min/max computation

Last post by mamorani « Fri Mar 12, 2021 8:08 pm

by mamorani » Fri Mar 12, 2021 8:08 pm

0 Replies

196 Views

Last post by mamorani
Fri Mar 12, 2021 8:08 pm
Complex datatype is not supported for this block, with divide

Last post by mamorani « Fri Mar 12, 2021 8:07 pm

by mamorani » Fri Mar 12, 2021 8:07 pm

0 Replies

195 Views

Last post by mamorani
Fri Mar 12, 2021 8:07 pm
Number of Gateway blocks and Simulink I/O ports in the top-level Xilinx subsystem must be the same.

Last post by mamorani « Fri Mar 12, 2021 8:07 pm

by mamorani » Fri Mar 12, 2021 8:07 pm

0 Replies

213 Views

Last post by mamorani
Fri Mar 12, 2021 8:07 pm
An output type of ufix128 is not supported in combination with Linear Interpolation by the Lookup Table (n-D) block for

Last post by mamorani « Fri Mar 12, 2021 8:06 pm

by mamorani » Fri Mar 12, 2021 8:06 pm

0 Replies

203 Views

Last post by mamorani
Fri Mar 12, 2021 8:06 pm
Trigonometric Function ' is not supported for HDL code generation.

Last post by mamorani « Fri Mar 12, 2021 8:06 pm

by mamorani » Fri Mar 12, 2021 8:06 pm

0 Replies

201 Views

Last post by mamorani
Fri Mar 12, 2021 8:06 pm
Approximate method for this block must be set to ''None'' for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 8:05 pm

by mamorani » Fri Mar 12, 2021 8:05 pm

0 Replies

210 Views

Last post by mamorani
Fri Mar 12, 2021 8:05 pm

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