Signal Processing

New Topic

3049 topics

Page 51 of 122
- Jump to page:
Previous
1
…
49
50
51
52
53
…
122
Next

Topics

Replies

Views

Last post

Invalid "IOPadConstraint" setting for interface "IOPadConstraint" must be a cell array in the format of " when all pin

Last post by mamorani « Fri Mar 12, 2021 10:33 pm

by mamorani » Fri Mar 12, 2021 10:33 pm

0 Replies

278 Views

Last post by mamorani
Fri Mar 12, 2021 10:33 pm
Invalid "FPGAPinMap" setting on interface . "FPGAPinMap" must be a cell array in the format of

Last post by mamorani « Fri Mar 12, 2021 10:33 pm

by mamorani » Fri Mar 12, 2021 10:33 pm

0 Replies

258 Views

Last post by mamorani
Fri Mar 12, 2021 10:33 pm
option is not supported by IP Core Generation workflow.

Last post by mamorani « Fri Mar 12, 2021 10:32 pm

by mamorani » Fri Mar 12, 2021 10:32 pm

0 Replies

265 Views

Last post by mamorani
Fri Mar 12, 2021 10:32 pm
When specifying "IOPadConstraint" for interface " " for each FPGA pin (in the format of the length of the "IOPadConstra

Last post by mamorani « Fri Mar 12, 2021 10:31 pm

by mamorani » Fri Mar 12, 2021 10:31 pm

0 Replies

276 Views

Last post by mamorani
Fri Mar 12, 2021 10:31 pm
Setting "Falling" for parameter "Clock Edge" is not supported in workflow.

Last post by mamorani « Fri Mar 12, 2021 10:31 pm

by mamorani » Fri Mar 12, 2021 10:31 pm

0 Replies

277 Views

Last post by mamorani
Fri Mar 12, 2021 10:31 pm
In HDL Workflow Advisor, please go to task 3.1.2 Set Advanced Options > Coding Standards, and uncheck the options

Last post by mamorani « Fri Mar 12, 2021 10:30 pm

by mamorani » Fri Mar 12, 2021 10:30 pm

0 Replies

327 Views

Last post by mamorani
Fri Mar 12, 2021 10:30 pm
failed to recognize rotate mode in elaboration

Last post by mamorani « Fri Mar 12, 2021 10:27 pm

by mamorani » Fri Mar 12, 2021 10:27 pm

0 Replies

280 Views

Last post by mamorani
Fri Mar 12, 2021 10:27 pm
Sum with more than two inputs must be a sum of elements; no subtraction permitted.

Last post by mamorani « Fri Mar 12, 2021 10:26 pm

by mamorani » Fri Mar 12, 2021 10:26 pm

0 Replies

290 Views

Last post by mamorani
Fri Mar 12, 2021 10:26 pm
Integer delay block has non-zero initial value and will not be mapped to RAM

Last post by mamorani « Fri Mar 12, 2021 10:26 pm

by mamorani » Fri Mar 12, 2021 10:26 pm

0 Replies

308 Views

Last post by mamorani
Fri Mar 12, 2021 10:26 pm
Port Numbering error in hdlparseportdims, expected number,integer} ports, actually parsed number,integer}

Last post by mamorani « Fri Mar 12, 2021 10:25 pm

by mamorani » Fri Mar 12, 2021 10:25 pm

0 Replies

333 Views

Last post by mamorani
Fri Mar 12, 2021 10:25 pm
The hdlsetup command requires a model to be specified. Use hdlsetup(''modelname'') instead

Last post by mamorani « Fri Mar 12, 2021 10:24 pm

by mamorani » Fri Mar 12, 2021 10:24 pm

0 Replies

286 Views

Last post by mamorani
Fri Mar 12, 2021 10:24 pm
License for ''HDL Verifier(TM)'' is not available or installation is incomplete.

Last post by mamorani « Fri Mar 12, 2021 10:24 pm

by mamorani » Fri Mar 12, 2021 10:24 pm

0 Replies

281 Views

Last post by mamorani
Fri Mar 12, 2021 10:24 pm
Invalid HDL Implementation Parameter for the block

Last post by mamorani « Fri Mar 12, 2021 10:23 pm

by mamorani » Fri Mar 12, 2021 10:23 pm

0 Replies

309 Views

Last post by mamorani
Fri Mar 12, 2021 10:23 pm
The read and write data types do not agree for RAM block

Last post by mamorani « Fri Mar 12, 2021 10:23 pm

by mamorani » Fri Mar 12, 2021 10:23 pm

0 Replies

282 Views

Last post by mamorani
Fri Mar 12, 2021 10:23 pm
Number of write address and write data ports do not agree for RAM block

Last post by mamorani « Fri Mar 12, 2021 10:22 pm

by mamorani » Fri Mar 12, 2021 10:22 pm

0 Replies

314 Views

Last post by mamorani
Fri Mar 12, 2021 10:22 pm
RAMDirective value ' does not apply to synthesis chip family Mapping to UltraRAM is only Trigonometric Function in bl

Last post by mamorani « Fri Mar 12, 2021 10:22 pm

by mamorani » Fri Mar 12, 2021 10:22 pm

0 Replies

270 Views

Last post by mamorani
Fri Mar 12, 2021 10:22 pm
RAMDirective value ' does not apply to synthesis chip family Mapping to UltraRAM is only supported only for devices th

Last post by mamorani « Fri Mar 12, 2021 10:21 pm

by mamorani » Fri Mar 12, 2021 10:21 pm

0 Replies

285 Views

Last post by mamorani
Fri Mar 12, 2021 10:21 pm
Invalid RAMDirective value specified for synthesis tool ' Mapping to RAM by using the value is supported only for

Last post by mamorani « Fri Mar 12, 2021 10:21 pm

by mamorani » Fri Mar 12, 2021 10:21 pm

0 Replies

271 Views

Last post by mamorani
Fri Mar 12, 2021 10:21 pm
The RAM block has initial value specified. To map to UltraRAM, update the initial value to '0', because all memory locat

Last post by mamorani « Fri Mar 12, 2021 10:20 pm

by mamorani » Fri Mar 12, 2021 10:20 pm

0 Replies

258 Views

Last post by mamorani
Fri Mar 12, 2021 10:20 pm
RAMDirective 'ultra' is not supported with the Dual Port RAM block. Dual Port RAM uses a ''write first'' mode which is n

Last post by mamorani « Fri Mar 12, 2021 10:20 pm

by mamorani » Fri Mar 12, 2021 10:20 pm

0 Replies

304 Views

Last post by mamorani
Fri Mar 12, 2021 10:20 pm
Enabling Industry mode will overwrite certain codegeneration options in a dominating way

Last post by mamorani « Fri Mar 12, 2021 10:19 pm

by mamorani » Fri Mar 12, 2021 10:19 pm

0 Replies

295 Views

Last post by mamorani
Fri Mar 12, 2021 10:19 pm
When ''InportSignals'' is specified, no need to specify ''inportNames'', ''inportType'' or ''inportRates'' in network

Last post by mamorani « Fri Mar 12, 2021 10:18 pm

by mamorani » Fri Mar 12, 2021 10:18 pm

0 Replies

297 Views

Last post by mamorani
Fri Mar 12, 2021 10:18 pm
found a double type, at line number in MATLAB Function Block

Last post by mamorani « Fri Mar 12, 2021 10:18 pm

by mamorani » Fri Mar 12, 2021 10:18 pm

0 Replies

287 Views

Last post by mamorani
Fri Mar 12, 2021 10:18 pm
The read and write address types do not agree for RAM block

Last post by mamorani « Fri Mar 12, 2021 10:17 pm

by mamorani » Fri Mar 12, 2021 10:17 pm

0 Replies

267 Views

Last post by mamorani
Fri Mar 12, 2021 10:17 pm
Number of read address and read data ports do not agree for RAM block

Last post by mamorani « Fri Mar 12, 2021 10:17 pm

by mamorani » Fri Mar 12, 2021 10:17 pm

0 Replies

241 Views

Last post by mamorani
Fri Mar 12, 2021 10:17 pm

New Topic

3049 topics

Page 51 of 122
- Jump to page:
Previous
1
…
49
50
51
52
53
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 1 guest

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum