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Cannot generate code for " because " is not installed. Please install the support package.

Last post by mamorani « Fri Mar 12, 2021 10:54 pm

by mamorani » Fri Mar 12, 2021 10:54 pm

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200 Views

Last post by mamorani
Fri Mar 12, 2021 10:54 pm
Option "split entity and architecture" is not supported in workflow

Last post by mamorani « Fri Mar 12, 2021 10:54 pm

by mamorani » Fri Mar 12, 2021 10:54 pm

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199 Views

Last post by mamorani
Fri Mar 12, 2021 10:54 pm
Setting "signed/unsigned" for parameter "Input data type" and "Output data type" is not supported in workflow

Last post by mamorani « Fri Mar 12, 2021 10:53 pm

by mamorani » Fri Mar 12, 2021 10:53 pm

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198 Views

Last post by mamorani
Fri Mar 12, 2021 10:53 pm
In HDL Workflow Advisor, please go to task 3.1.2 Set Advanced Options > Additional settings > Ports, and change the para

Last post by mamorani « Fri Mar 12, 2021 10:53 pm

by mamorani » Fri Mar 12, 2021 10:53 pm

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261 Views

Last post by mamorani
Fri Mar 12, 2021 10:53 pm
A resettable timing controller is not supported in the workflow. To correct this issue, run ''hdlset_param( ''TimingC

Last post by mamorani « Fri Mar 12, 2021 10:52 pm

by mamorani » Fri Mar 12, 2021 10:52 pm

0 Replies

178 Views

Last post by mamorani
Fri Mar 12, 2021 10:52 pm
Setting "Active-low" for parameter "Reset asserted level" is not supported in workflow.

Last post by mamorani « Fri Mar 12, 2021 10:52 pm

by mamorani » Fri Mar 12, 2021 10:52 pm

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258 Views

Last post by mamorani
Fri Mar 12, 2021 10:52 pm
In HDL Workflow Advisor, please go to task HDL Code Generation > Clocks & Ports > Clocks, and change the parameter "Rese

Last post by mamorani « Fri Mar 12, 2021 10:51 pm

by mamorani » Fri Mar 12, 2021 10:51 pm

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213 Views

Last post by mamorani
Fri Mar 12, 2021 10:51 pm
Interfaces are required to be assigned, please assign these interfaces to subsystem ports in the Target Interface Tab

Last post by mamorani « Fri Mar 12, 2021 10:51 pm

by mamorani » Fri Mar 12, 2021 10:51 pm

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240 Views

Last post by mamorani
Fri Mar 12, 2021 10:51 pm
Interface is required to be assigned, please assign this interface to one of the ports in the Target Interface Table

Last post by mamorani « Fri Mar 12, 2021 10:50 pm

by mamorani » Fri Mar 12, 2021 10:50 pm

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244 Views

Last post by mamorani
Fri Mar 12, 2021 10:50 pm
Minimize global resets" is not supported in workflow. It is only supported in the Generic FPGA/ASIC workflow

Last post by mamorani « Fri Mar 12, 2021 10:50 pm

by mamorani » Fri Mar 12, 2021 10:50 pm

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229 Views

Last post by mamorani
Fri Mar 12, 2021 10:50 pm
In HDL Workflow Advisor, please go to task 3.1.3 Set Optimization Options > General, and uncheck the parameter "Minimize

Last post by mamorani « Fri Mar 12, 2021 10:49 pm

by mamorani » Fri Mar 12, 2021 10:49 pm

0 Replies

214 Views

Last post by mamorani
Fri Mar 12, 2021 10:49 pm
Board name in registration file mismatches with the board name in its parent board plugin.

Last post by mamorani « Fri Mar 12, 2021 10:49 pm

by mamorani » Fri Mar 12, 2021 10:49 pm

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211 Views

Last post by mamorani
Fri Mar 12, 2021 10:49 pm
Switching reference design to causes incompatible interface assignment on following ports. The interface setting on th

Last post by mamorani « Fri Mar 12, 2021 10:48 pm

by mamorani » Fri Mar 12, 2021 10:48 pm

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212 Views

Last post by mamorani
Fri Mar 12, 2021 10:48 pm
Specified reference design folder does not contain the C/C++ source files folder nPlease make sure you have all the f

Last post by mamorani « Fri Mar 12, 2021 10:39 pm

by mamorani » Fri Mar 12, 2021 10:39 pm

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225 Views

Last post by mamorani
Fri Mar 12, 2021 10:39 pm
The path to reference design folder is either empty or does not exist

Last post by mamorani « Fri Mar 12, 2021 10:38 pm

by mamorani » Fri Mar 12, 2021 10:38 pm

0 Replies

241 Views

Last post by mamorani
Fri Mar 12, 2021 10:38 pm
Board name in reference design mismatches with the board name in its parent board plugin

Last post by mamorani « Fri Mar 12, 2021 10:38 pm

by mamorani » Fri Mar 12, 2021 10:38 pm

0 Replies

227 Views

Last post by mamorani
Fri Mar 12, 2021 10:38 pm
Input is not a cell array of character vectors.\nA cell array of character vectors is a cell array where every element i

Last post by mamorani « Fri Mar 12, 2021 10:38 pm

by mamorani » Fri Mar 12, 2021 10:38 pm

0 Replies

203 Views

Last post by mamorani
Fri Mar 12, 2021 10:38 pm
Target Interface Table needs to be populated before generating FPGA top level wrapper.

Last post by mamorani « Fri Mar 12, 2021 10:37 pm

by mamorani » Fri Mar 12, 2021 10:37 pm

0 Replies

227 Views

Last post by mamorani
Fri Mar 12, 2021 10:37 pm
Target Platform needs to be specified before generating FPGA top level wrapper.

Last post by mamorani « Fri Mar 12, 2021 10:37 pm

by mamorani » Fri Mar 12, 2021 10:37 pm

0 Replies

210 Views

Last post by mamorani
Fri Mar 12, 2021 10:37 pm
Setting "Multiple" for parameter "Clock inputs" is not supported in workflow

Last post by mamorani « Fri Mar 12, 2021 10:36 pm

by mamorani » Fri Mar 12, 2021 10:36 pm

0 Replies

218 Views

Last post by mamorani
Fri Mar 12, 2021 10:36 pm
In HDL Workflow Advisor, please go to task 3.1.2 Set Advanced Options > Clock settings, and change the parameter "Clock

Last post by mamorani « Fri Mar 12, 2021 10:36 pm

by mamorani » Fri Mar 12, 2021 10:36 pm

0 Replies

239 Views

Last post by mamorani
Fri Mar 12, 2021 10:36 pm
Minimize clock enables" is not supported in workflow

Last post by mamorani « Fri Mar 12, 2021 10:36 pm

by mamorani » Fri Mar 12, 2021 10:36 pm

0 Replies

212 Views

Last post by mamorani
Fri Mar 12, 2021 10:36 pm
In HDL Workflow Advisor, please go to task 3.1.2 Set Advanced Options > Additional settings > Optimization, and uncheck

Last post by mamorani « Fri Mar 12, 2021 10:35 pm

by mamorani » Fri Mar 12, 2021 10:35 pm

0 Replies

208 Views

Last post by mamorani
Fri Mar 12, 2021 10:35 pm
Reference design for tool version is available

Last post by mamorani « Fri Mar 12, 2021 10:34 pm

by mamorani » Fri Mar 12, 2021 10:34 pm

0 Replies

234 Views

Last post by mamorani
Fri Mar 12, 2021 10:34 pm
Unable to locate valid embedded system reference design for platform which support current interface mapping. Without v

Last post by mamorani « Fri Mar 12, 2021 10:34 pm

by mamorani » Fri Mar 12, 2021 10:34 pm

0 Replies

234 Views

Last post by mamorani
Fri Mar 12, 2021 10:34 pm

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