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Industry rules require the package file name postfix to be Overriding user setting

Last post by mamorani « Fri Mar 12, 2021 11:10 pm

by mamorani » Fri Mar 12, 2021 11:10 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 11:10 pm
Non-synthesizable fixed or floating point construct found in design

Last post by mamorani « Fri Mar 12, 2021 11:09 pm

by mamorani » Fri Mar 12, 2021 11:09 pm

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413 Views

Last post by mamorani
Fri Mar 12, 2021 11:09 pm
No messages, warnings, or errors were found

Last post by mamorani « Fri Mar 12, 2021 11:09 pm

by mamorani » Fri Mar 12, 2021 11:09 pm

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515 Views

Last post by mamorani
Fri Mar 12, 2021 11:09 pm
Masked parameter/generic name is longer than specified

Last post by mamorani « Fri Mar 12, 2021 11:08 pm

by mamorani » Fri Mar 12, 2021 11:08 pm

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231 Views

Last post by mamorani
Fri Mar 12, 2021 11:08 pm
VHDL file extension is '. Valid extensions are ''.vhd'' or ''.vhdl''

Last post by mamorani « Fri Mar 12, 2021 11:07 pm

by mamorani » Fri Mar 12, 2021 11:07 pm

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255 Views

Last post by mamorani
Fri Mar 12, 2021 11:07 pm
Constant block has ''Value'' set to ''X'' or ''Z'', which is not recommended for HDL synthesis. In the HDL Block Propert

Last post by mamorani « Fri Mar 12, 2021 11:07 pm

by mamorani » Fri Mar 12, 2021 11:07 pm

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255 Views

Last post by mamorani
Fri Mar 12, 2021 11:07 pm
HDL configuration parameter 'ResetType' is set to 'asynchronous'; the coding standard customization rule requires settin

Last post by mamorani « Fri Mar 12, 2021 11:06 pm

by mamorani » Fri Mar 12, 2021 11:06 pm

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244 Views

Last post by mamorani
Fri Mar 12, 2021 11:06 pm
'MinimizeClockEnables' parameter is set to 'off', but coding standard customization overrides it to 'on

Last post by mamorani « Fri Mar 12, 2021 11:05 pm

by mamorani » Fri Mar 12, 2021 11:05 pm

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295 Views

Last post by mamorani
Fri Mar 12, 2021 11:05 pm
Testpoint support in HDL code generation' is enabled during code generation. This will result in additional output ports

Last post by mamorani « Fri Mar 12, 2021 11:05 pm

by mamorani » Fri Mar 12, 2021 11:05 pm

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238 Views

Last post by mamorani
Fri Mar 12, 2021 11:05 pm
Unknown field(s) set for coding standard customization object property

Last post by mamorani « Fri Mar 12, 2021 11:05 pm

by mamorani » Fri Mar 12, 2021 11:05 pm

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262 Views

Last post by mamorani
Fri Mar 12, 2021 11:05 pm
Invalid value set for coding standard customization object property on the field Value should be a finite and positive

Last post by mamorani « Fri Mar 12, 2021 11:04 pm

by mamorani » Fri Mar 12, 2021 11:04 pm

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249 Views

Last post by mamorani
Fri Mar 12, 2021 11:04 pm
HDL Coder internal object not found (inconsistent state reached) when HDLCodingStandard is set to Industry

Last post by mamorani « Fri Mar 12, 2021 11:04 pm

by mamorani » Fri Mar 12, 2021 11:04 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 11:04 pm
Unknown target language used when HDLCodingStandard is set to Industry.

Last post by mamorani « Fri Mar 12, 2021 11:04 pm

by mamorani » Fri Mar 12, 2021 11:04 pm

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266 Views

Last post by mamorani
Fri Mar 12, 2021 11:04 pm
Industry Compliance report with errors, warnings, messages

Last post by mamorani « Fri Mar 12, 2021 11:03 pm

by mamorani » Fri Mar 12, 2021 11:03 pm

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247 Views

Last post by mamorani
Fri Mar 12, 2021 11:03 pm
Setting "Generic RAM without clock enable" for parameter "RAM Architecture" is not supported in workflow

Last post by mamorani « Fri Mar 12, 2021 11:02 pm

by mamorani » Fri Mar 12, 2021 11:02 pm

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346 Views

Last post by mamorani
Fri Mar 12, 2021 11:02 pm
Conflicting interface display text detected between interface and interface

Last post by mamorani « Fri Mar 12, 2021 11:02 pm

by mamorani » Fri Mar 12, 2021 11:02 pm

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266 Views

Last post by mamorani
Fri Mar 12, 2021 11:02 pm
Xilinx System Generator block is not supported in IP Core Generation Workflow.

Last post by mamorani « Fri Mar 12, 2021 11:01 pm

by mamorani » Fri Mar 12, 2021 11:01 pm

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263 Views

Last post by mamorani
Fri Mar 12, 2021 11:01 pm
Verilog code generation is not supported in workflow.

Last post by mamorani « Fri Mar 12, 2021 11:01 pm

by mamorani » Fri Mar 12, 2021 11:01 pm

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254 Views

Last post by mamorani
Fri Mar 12, 2021 11:01 pm
In HDL Workflow Advisor, please go to task 3.1.1 Set Basic Options > Target, and change the parameter "Language

Last post by mamorani « Fri Mar 12, 2021 11:00 pm

by mamorani » Fri Mar 12, 2021 11:00 pm

0 Replies

251 Views

Last post by mamorani
Fri Mar 12, 2021 11:00 pm
Reference Design " does not support assigned interface

Last post by mamorani « Fri Mar 12, 2021 11:00 pm

by mamorani » Fri Mar 12, 2021 11:00 pm

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279 Views

Last post by mamorani
Fri Mar 12, 2021 11:00 pm
Top-level port ' is a Bus, which is not supported in the workflow

Last post by mamorani « Fri Mar 12, 2021 10:59 pm

by mamorani » Fri Mar 12, 2021 10:59 pm

0 Replies

357 Views

Last post by mamorani
Fri Mar 12, 2021 10:59 pm
Please change your tool version, or use a different reference design. If you want to attempt to continue using this refe

Last post by mamorani « Fri Mar 12, 2021 10:59 pm

by mamorani » Fri Mar 12, 2021 10:59 pm

0 Replies

225 Views

Last post by mamorani
Fri Mar 12, 2021 10:59 pm
Using incompatible tool version, HDL Workflow Advisor may not be able to run task "Embedded System Integration -> Create

Last post by mamorani « Fri Mar 12, 2021 10:58 pm

by mamorani » Fri Mar 12, 2021 10:58 pm

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249 Views

Last post by mamorani
Fri Mar 12, 2021 10:58 pm
This reference design is compatible with tool version

Last post by mamorani « Fri Mar 12, 2021 10:58 pm

by mamorani » Fri Mar 12, 2021 10:58 pm

0 Replies

281 Views

Last post by mamorani
Fri Mar 12, 2021 10:58 pm
Current reference design may not be compatible with the version of " tool on system path.

Last post by mamorani « Fri Mar 12, 2021 10:57 pm

by mamorani » Fri Mar 12, 2021 10:57 pm

0 Replies

273 Views

Last post by mamorani
Fri Mar 12, 2021 10:57 pm

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