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Do not use nonblocking assignments for assigning initial values in always construct for sequential circuits

Last post by mamorani « Fri Mar 12, 2021 11:58 pm

by mamorani » Fri Mar 12, 2021 11:58 pm

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Last post by mamorani
Fri Mar 12, 2021 11:58 pm
nonblocking assignment should not be used in combinational always blocks.

Last post by mamorani « Fri Mar 12, 2021 11:58 pm

by mamorani » Fri Mar 12, 2021 11:58 pm

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299 Views

Last post by mamorani
Fri Mar 12, 2021 11:58 pm
Do not use wait statement in process statements (Sensitivity list should be used).

Last post by mamorani « Fri Mar 12, 2021 11:58 pm

by mamorani » Fri Mar 12, 2021 11:58 pm

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279 Views

Last post by mamorani
Fri Mar 12, 2021 11:58 pm
At least one event expression must be described for an always construct.

Last post by mamorani « Fri Mar 12, 2021 11:57 pm

by mamorani » Fri Mar 12, 2021 11:57 pm

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271 Views

Last post by mamorani
Fri Mar 12, 2021 11:57 pm
Multiple event Expressions should not be described with always constructs..

Last post by mamorani « Fri Mar 12, 2021 11:57 pm

by mamorani » Fri Mar 12, 2021 11:57 pm

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311 Views

Last post by mamorani
Fri Mar 12, 2021 11:57 pm
Do not define constants in the sensitivity list.

Last post by mamorani « Fri Mar 12, 2021 11:57 pm

by mamorani » Fri Mar 12, 2021 11:57 pm

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323 Views

Last post by mamorani
Fri Mar 12, 2021 11:57 pm
A variable specified in the sensitivity list must be read in the contained block.

Last post by mamorani « Fri Mar 12, 2021 11:56 pm

by mamorani » Fri Mar 12, 2021 11:56 pm

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314 Views

Last post by mamorani
Fri Mar 12, 2021 11:56 pm
Check latch creation from RTL lint checker and synthesis tools; Rules for always Constructs of Combinational Logic Desig

Last post by mamorani « Fri Mar 12, 2021 11:55 pm

by mamorani » Fri Mar 12, 2021 11:55 pm

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261 Views

Last post by mamorani
Fri Mar 12, 2021 11:55 pm
Do not assign state encoding by attaching attributes to the state variable which is declared as a type

Last post by mamorani « Fri Mar 12, 2021 11:55 pm

by mamorani » Fri Mar 12, 2021 11:55 pm

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307 Views

Last post by mamorani
Fri Mar 12, 2021 11:55 pm
Ensure that the sequential and combinational parts of an FSM description should be in separate always blocks.

Last post by mamorani « Fri Mar 12, 2021 11:55 pm

by mamorani » Fri Mar 12, 2021 11:55 pm

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253 Views

Last post by mamorani
Fri Mar 12, 2021 11:55 pm
Number of states of an FSM should be within 40.

Last post by mamorani « Fri Mar 12, 2021 11:54 pm

by mamorani » Fri Mar 12, 2021 11:54 pm

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312 Views

Last post by mamorani
Fri Mar 12, 2021 11:54 pm
If right side of the division or modulus operator is not a power of two, keep it within 8 bits.

Last post by mamorani « Fri Mar 12, 2021 11:54 pm

by mamorani » Fri Mar 12, 2021 11:54 pm

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354 Views

Last post by mamorani
Fri Mar 12, 2021 11:54 pm
Keep the left side of the division or modulus operator within 12 bits

Last post by mamorani « Fri Mar 12, 2021 11:53 pm

by mamorani » Fri Mar 12, 2021 11:53 pm

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292 Views

Last post by mamorani
Fri Mar 12, 2021 11:53 pm
Do not use arithmetic and logical expressions at the right and left sides of the division or modules operator

Last post by mamorani « Fri Mar 12, 2021 11:53 pm

by mamorani » Fri Mar 12, 2021 11:53 pm

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298 Views

Last post by mamorani
Fri Mar 12, 2021 11:53 pm
Common operational expressions should be described explicitly.

Last post by mamorani « Fri Mar 12, 2021 11:52 pm

by mamorani » Fri Mar 12, 2021 11:52 pm

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276 Views

Last post by mamorani
Fri Mar 12, 2021 11:52 pm
Large multipliers of bits or larger, must not be described using the multiplication operator with RTL

Last post by mamorani « Fri Mar 12, 2021 11:52 pm

by mamorani » Fri Mar 12, 2021 11:52 pm

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286 Views

Last post by mamorani
Fri Mar 12, 2021 11:52 pm
Do not use any arithmetic operator thrice or more in the same "if" statement, avoiding resource sharing

Last post by mamorani « Fri Mar 12, 2021 11:52 pm

by mamorani » Fri Mar 12, 2021 11:52 pm

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284 Views

Last post by mamorani
Fri Mar 12, 2021 11:52 pm
Function To_stdlogicvector should not be used in the design.

Last post by mamorani « Fri Mar 12, 2021 11:51 pm

by mamorani » Fri Mar 12, 2021 11:51 pm

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284 Views

Last post by mamorani
Fri Mar 12, 2021 11:51 pm
Signed data type must be used in signed operation and std_logic_vector calling std_logic_unsigned package must be used i

Last post by mamorani « Fri Mar 12, 2021 11:51 pm

by mamorani » Fri Mar 12, 2021 11:51 pm

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298 Views

Last post by mamorani
Fri Mar 12, 2021 11:51 pm
Integer objects must not be assigned negative values.

Last post by mamorani « Fri Mar 12, 2021 11:51 pm

by mamorani » Fri Mar 12, 2021 11:51 pm

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373 Views

Last post by mamorani
Fri Mar 12, 2021 11:51 pm
Take care of comparing negative value integer variables and reg, wire variables

Last post by mamorani « Fri Mar 12, 2021 11:50 pm

by mamorani » Fri Mar 12, 2021 11:50 pm

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318 Views

Last post by mamorani
Fri Mar 12, 2021 11:50 pm
Take care of bit width in assigning integer to reg or wire

Last post by mamorani « Fri Mar 12, 2021 11:50 pm

by mamorani » Fri Mar 12, 2021 11:50 pm

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304 Views

Last post by mamorani
Fri Mar 12, 2021 11:50 pm
Bit-widths of operands of a relational operator should match

Last post by mamorani « Fri Mar 12, 2021 11:50 pm

by mamorani » Fri Mar 12, 2021 11:50 pm

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292 Views

Last post by mamorani
Fri Mar 12, 2021 11:50 pm
Do not use RAM output signals for a conditional expression of if statements

Last post by mamorani « Fri Mar 12, 2021 11:49 pm

by mamorani » Fri Mar 12, 2021 11:49 pm

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390 Views

Last post by mamorani
Fri Mar 12, 2021 11:49 pm
Do not assign 'X' except for the others clause of case statements.

Last post by mamorani « Fri Mar 12, 2021 11:48 pm

by mamorani » Fri Mar 12, 2021 11:48 pm

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247 Views

Last post by mamorani
Fri Mar 12, 2021 11:48 pm

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